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Multi-level look-ahead for high speed arithmetic operation over
long word lengths
PIN CONFIGURATION
G1
P1
G0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
P2
G2
Cn
Cn+x
Cn+y
G
Cn+z
DESCRIPTION
The 74F182 is a high speed carry look-ahead generator. It accepts
up to four pairs of active-Low Carry Propagate (P0, P1, P2, P3) and
Carry Generate (G0, G1, G2, G3) signals and an active-High Carry
input (Cn) and provides anticipated active-High carries (Cn+x, Cn+y,
Cn+z) across four groups of binary adders. The 74F182 also has
active-Low Carry Propagate (P) Carry Generate (G) outputs which
may be used for further levels of look-ahead.
The logic equations provided at the outputs are:
Cn+x = G0+P0Cn
Cn+y = G1+P1G0+P1P0Cn
Cn+z = G2+P2G1+P2P1G0+P2P1P0Cn
G = G3+P3G2+P3P2G1+P3P2P1G0
P = P3P2P1P0
The 74F182 can also be used with binary ALUs in an active-Low or
active-High input operand mode. The connections to and from the
ALU to the carry look-ahead generator are identical in both cases.
P0
G3
P3
P
GND
SF00725
TYPE
74F182
TYPICAL
PROPAGATION
DELAY
5.0ns
TYPICAL
SUPPLY CURRENT
(TOTAL)
21mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
16-pin plastic DIP
16-pin plastic SO
COMMERCIAL RANGE
V
CC
= 5V
鹵10%,
T
amb
= 0擄C to +70擄C
N74F182N
N74F182D
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
Cn
G0, G2
G1
G3
P0, P1
P2
P3
Cn+x鈥揅n+z
G
P
Carry input
Carry generate inputs (active-Low)
Carry generate input (active-Low)
Carry generate input (active-Low)
Carry propagate inputs (active-Low)
Carry propagate input (active-Low)
Carry propagate input (active-Low)
Carry outputs
Carry generate output (active-Low)
Carry propagate output (active-Low)
DESCRIPTION
74FAST (U.L.) HIGH/LOW
2.5/2.0
2.5/14.0
2.5/16.0
2.5/8.0
2.5/8.0
2.5/6.0
2.5/4.0
50/33
50/33
50/33
LOAD VALUE HIGH/LOW
50碌A(chǔ)/1.2mA
50碌A(chǔ)/8.4mA
50碌A(chǔ)/9.6mA
50碌A(chǔ)/4.8mA
50碌A(chǔ)/4.8mA
50碌A(chǔ)/3.6mA
50碌A(chǔ)/2.4mA
1.0mA/20mA
1.0mA/20mA
1.0mA/20mA
NOTE:
One (1.0) FAST unit load is defined as: 20碌A(chǔ) in the High state and 0.6mA in the Low state.
1991 Apr 15
2
853鈥?161 02162