Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flop
with common clock and reset
74F114
DESCRIPTION
The 74F114, Dual Negative edge-triggered JK-Type Flip-Flop with
common clock and reset inputs, features individual J, K, Clock (CP),
Set (SD) and Reset (RD) inputs, true and complementary outputs.
The SD and RD inputs, when Low, set or reset the outputs as shown
in the Function Table regardless of the level at the other inputs.
A High level on the clock (CP) input enables the J and K inputs and
data will be accepted. The logic levels and data will be accepted.
The logic levels at the J and K inputs may be allowed to change
while the CP is High and flip-flop will perform according to the
Function Table as long as minimum setup and hold times are
observed. Output changes are initiated by the High-to-Low transition
of the CP.
TYPICAL
SUPPLY CURRENT
(TOTAL)
15mA
PIN CONFIGURATION
RD
K0
J0
SD0
Q0
Q0
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
CP
K1
J1
SD1
Q1
Q1
SF00110
ORDERING INFORMATION
DESCRIPTION
14-pin plastic DIP
14-pin plastic SO
COMMERCIAL RANGE
V
CC
= 5V
鹵10%,
T
amb
= 0擄C to +70擄C
N74F114N
N74F114D
PKG. DWG. #
SOT27-1
SOT108-1
TYPE
74F114
TYPICAL f
MAX
100MHz
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
J0, J1
K0, K1
SD0, SD1
RD
CP
Q0, Q0; Q1, Q1
J inputs
K inputs
Set inputs (active Low)
Reset input (active Low)
Clock Pulse input (active falling edge)
Data outputs
DESCRIPTION
74F (U.L.) HIGH/LOW
1.0/1.0
1.0/1.0
1.0/5.0
1.0/10.0
1.0/8.0
50/33
LOAD VALUE HIGH/LOW
20碌A(chǔ)/0.6mA
20碌A(chǔ)/0.6mA
20碌A(chǔ)/3.0mA
20碌A(chǔ)/6.0mA
20碌A(chǔ)/4.8mA
1.0mA/20mA
NOTE:
One (1.0) FAST unit load is defined as: 20碌A(chǔ) in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
3
11
2
12
IEC/IEEE SYMBOL
1
13
J0
13
4
1
10
CP
SD0
RD0
SD1
Q0
Q0
Q1
Q1
10
11
12
5
V
CC
= Pin 14
GND = Pin 7
6
9
8
J1
K0
K1
4
3
2
R
C1
S
1K
1J
5
6
9
8
SF00111
SF00112
1996 Mar 14
1
853鈥?340 16572
1
2
3
4
5
6
