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MX98224EC Datasheet

  • MX98224EC

  • 24-port Dual-Speed Ethernet Switch Controller

  • 269.62KB

  • 38頁(yè)

  • ETC

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PRELIMINARY
MX98224EC
24-port Dual-Speed Ethernet Switch Controller
FEATURES
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Single chip 24-port 10/100M wire speed Ethernet
switching controller with all memory embedded
Integration of 24-port dual speed, full/half duplex
capable Media Access Controllers (MACs) with RMII
interfaces
Support IEEE 802.3x compliant flow control for FDX
and back-pressure flow control for HDX
Auto-negotiation through MDC/MDIO
Support source/destination MAC address lookup and
aging within built-in storage of 8K MAC address (4K
entries each entry table)
Self address learning, forwarding, and filtering
schemes
Store-and-Forward switching operation
12-group port base VLAN with port overlapping
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IEEE 802.1q CoS and two priority queues support
based on port, tagging, and TOS configurations
Address table and PHY register access allowed
through CPU processor
Dynamic buffer management
No head-of-line blocking system support
Power on self diagnostic
Serial EEPROM (93C46) interface for auto-
configuration
Broadcast storm prevention
Serial CPU interface support for system configuration
required
Three alter/self-diagnostic LED interface
CMOS, 1.8/3.3V I/O tolerance
208 PQFP package
GENERAL DESCRIPTION
MX98224EC is a stand-alone 10/100M Ethernet switch
controller with SRAM embedded which saves 2-3 extra
64KX64 SRAM cost. Any standalone desktop or
enterprising Ethernet switches can be achieved by
simply combining MX98224EC and quad/octal physical
devices. All 24 ports are full duplex capable to provide
dedicated 20/200M bandwidth connections each port.
MX98224EC basically supports store-and-forward
switching scheme with two address entry tables, 4K size
each. The function modules integrated in controller
include 24-port half/full-duplex compatible media access
controller with RMII interface, address resolution logic
(ARL) for address learning, filtering, recognition, priority
queue manager, port base VLAN. It fully complies with
IEEE Std. 802.3/802.3u/802.1q specifications and
supports MDC/MDIO interface for physical layer
management with industrial standard physical devices.
The switch architecture adopting dynamic buffer
management shared by 24 ports can reach full-line
speed of high performance application.
To save
system cost, single 50Mhz clock is for RMII and system
requirement. MX98224EC proceeds in advanced
foundry and smaller package which consumes lower
power dissipation.
The smart features with low power CPU or EEPROM
are for system configuration and ALR access required.
Also, it emphasizes at Class of Service (CoS) which
extracts various packet types in appropriate forwarding
scheme. Now, Voice over IP (VoIP) is applied the
feature for cutting voice packet latency and promise the
quality of service. In addition, port-base VLAN is
another valuable feature for the switches. MX98224EC
offers 12 groups with port overlapping allowed. The
feature can add on more security and data flow in the
same switch with different groups should get connection
through router. The powerful switching architecture
and robust design can easily reach high performance,
non-blocking data flow.
Head-of-line blocking prevents switch performance, and
operation defective from other port impacts. The switch
architecture provides a clean port independent
operation.
It guarantees port transmission or receive
is not affected by other ports.
Moreover, user can discard broadcast packets regarding
the threshold of system overload.
This prevents
potential broadcast storming from abnormal events.
After buffer fullness drops in the safe margin, the switch
controller jumps into flow control state to allow physical
ports work as normal condition.
MX98224EC provides self on test as soon as power on
or reset. It will detect all buffer memory and address
table and others. If defective, LED is automatically on.
Several LEDs are defined in switch controller like status
of broadcast storm, packet loss, and buffer full.
P/N:PM0782
1
REV. 0.2, Apr, 18, 2001

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