鈥?/div>
High Speed: tPD = 3.8ns (Typ) at VCC = 5V
Low Power Dissipation: ICC = 2碌A(chǔ) (Max) at TA = 25擄C
High Noise Immunity: VNIH = VNIL = 28% VCC
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2V to 5.5V Operating Range
Low Noise: VOLP = 0.8V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300mA
ESD Performance: HBM > 2000V; Machine Model > 200V
Chip Complexity: 36 FETs or 9 Equivalent Gates
MC74VHC04
D SUFFIX
14鈥揕EAD SOIC PACKAGE
CASE 751A鈥?3
DT SUFFIX
14鈥揕EAD TSSOP PACKAGE
CASE 948G鈥?1
LOGIC DIAGRAM
1
2
M SUFFIX
14鈥揕EAD SOIC EIAJ PACKAGE
CASE 965鈥?1
A1
Y1
ORDERING INFORMATION
MC74VHCXXD
MC74VHCXXDT
MC74VHCXXM
SOIC
TSSOP
SOIC EIAJ
A2
3
4
Y2
A3
5
6
Y3
Y=A
FUNCTION TABLE
Inputs
A
L
H
Outputs
Y
H
L
A4
9
8
Y4
A5
11
10
Y5
A6
13
12
Y6
Pinout: 14鈥揕ead Packages
(Top View)
VCC
14
A6
13
Y6
12
A5
11
Y5
10
A4
9
Y4
8
1
A1
2
Y1
3
A2
4
Y2
5
A3
6
Y3
7
GND
6/97
漏
Motorola, Inc. 1997
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REV 1