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MX29F004TQI-55 Datasheet

  • MX29F004TQI-55

  • EEPROM

  • 39頁

  • ETC

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MX29F004T/B
4M-BIT [512KX8] CMOS FLASH MEMORY
FEATURES
鈥?524,288 x 8 only
鈥?Single power supply operation
- 5.0V only operation for read, erase and program op-
eration
鈥?Fast access time: 70/90/120ns
鈥?Low power consumption
- 30mA maximum active current (5MHz)
- 1uA typical standby current
鈥?Command register architecture
- Byte Programming (7us typical)
- Sector Erase
(Sector structure:16KB/8KB/8KB/32KB and 64KBx7)
鈥?Auto Erase (chip & sector) and Auto Program
- Automatically erase any combination of sectors with
Erase Suspend capability.
- Automatically program and verify data at specified
address
鈥?Erase suspend/Erase Resume
- Suspends an erase operation to read data from, or
program data to, another sector that is not being
erased, then resumes the erase.
鈥?Status Reply
- Data polling & Toggle bit for detection of program
and erase cycle completion.
鈥?Chip protect/unprotect for 5V only system or 5V/12V
system.
鈥?100,000 minimum erase/program cycles
鈥?Latch-up protected to 100mA from -1V to VCC+1V
鈥?Low VCC write inhibit is equal to or less than 3.2V
鈥?Package type:
- 32-pin PLCC, TSOP or PDIP
鈥?Compatibility with JEDEC standard
- Pinout and software compatible with single-power
supply Flash
鈥?20 years data retention
GENERAL DESCRIPTION
The MX29F004T/B is a 4-mega bit Flash memory orga-
nized as 512K bytes of 8 bits. MXIC's Flash memories
offer the most cost-effective and reliable read/write non-
volatile random access memory. The MX29F004T/B is
packaged in 32-pin PLCC, TSOP, PDIP. It is designed
to be reprogrammed and erased in system or in stan-
dard EPROM programmers.
The standard MX29F004T/B offers access time as fast
as 70ns, allowing operation of high-speed microproces-
sors without wait states. To eliminate bus contention,
the MX29F004T/B has separate chip enable (CE) and
output enable (OE) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29F004T/B uses a command register to manage this
functionality. The command register allows for 100%
TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining maxi-
mum EPROM compatibility.
MXIC Flash technology reliably stores memory
contents even after 100,000 erase and program
cycles. The MXIC cell is designed to optimize the
erase and programming mechanisms. In addition,
the combination of advanced tunnel oxide
processing and low internal electric fields for erase
and program operations produces reliable cycling.
The MX29F004T/B uses a 5.0V鹵10% VCC supply
to perform the High Reliability Erase and auto
Program/Erase algorithms.
The highest degree of latch-up protection is
achieved with MXIC's proprietary non-epi process.
Latch-up protection is proved for stresses up to 100
milliamps on address and data pin from -1V to VCC
+ 1V.
P/N:PM0554
REV. 1.6, JUL. 18, 2002
1

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