鈥?/div>
鈥?Status Reply
- Data polling & Toggle bit for detection of program
and erase cycle completion.
鈥?Chip protect/unprotect for 5V only system or 5V/12V
system
鈥?100,000 minimum erase/program cycles
鈥?Latch-up protected to 100mA from -1 to VCC+1V
鈥?Boot Code Sector Architecture
- T = Top Boot Sector
- B = Bottom Boot Sector
鈥?Low VCC write inhibit is equal to or less than 3.2V
鈥?Package type:
- 32-pin PLCC
- 32-pin TSOP
- 32-pin PDIP
鈥?Boot Code Sector Architecture
- T=Top Boot Sector
- B=Bottom Boot Sector
鈥?20 years data retention
GENERAL DESCRIPTION
The MX29F001T/B is a 1-mega bit Flash memory
organized as 128K bytes of 8 bits only MXIC's
Flash memories offer the most cost-effective and
reliable read/write non-volatile random access
memory. The MX29F001T/B is packaged in 32-pin
PLCC, TSOP, PDIP. It is designed to be repro-
grammed and erased in-system or in-standard
EPROM programmers.
The standard MX29F001T/B offers access time as
fast as 55ns, allowing operation of high-speed
microprocessors without wait states. To eliminate
bus contention, the MX29F001T/B has separate
chip enable (CE) and output enable (OE) controls.
MXIC's Flash memories augment EPROM function-
ality with in-circuit electrical erasure and
programming. The MX29F001T/B uses a command
register to manage this functionality. The command
register allows for 100% TTL level control inputs
and fixed power supply levels during erase and
programming, while maintaining maximum EPROM
compatibility.
MXIC Flash technology reliably stores memory con-
tents even after 100,000 erase and program cycles.
The MXIC cell is designed to optimize the erase and
programming mechanisms. In addition, the combi-
nation of advanced tunnel oxide processing and low
internal electric fields for erase and programming
operations produces reliable cycling.
The
MX29F001T/B uses a 5.0V
鹵
10% VCC supply to
perform the High Reliability Erase and auto
Program/Erase algorithms.
The highest degree of latch-up protection is
achieved with MXIC's proprietary non-epi process.
Latch-up protection is proved for stresses up to 100
milliamps on address and data pin from -1V to VCC
+ 1V.
P/N: PM0515
REV. 2.3, JUL. 09, 2002
1