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Communications
廬
Controller
for MIPS Processor
MV96340
The Marvell
簍
Horizon陋 MV96340 communications controller is the third generation of the industry-leading
Horizon陋 solution for converged applications including integrated access devices, edge routers, media gateways,
and Voice-over-IP (VoIP) equipment. Based on the Marvell Discovery陋-II system controllers, the Horizon
MV96340 communications controller integrates a MIPS
簍
SysAD bus interface, a DDR SDRAM memory
controller, dual 32-bit /single 64-bit PCI/PCI-X bridges, two 10/100/1000 Ethernet Media Access Controllers
(MACs) with a set of eight, high-speed, multi-protocol WAN interfaces, and a NetGX陋 co-processor, supported
by a full set of security, ATM and packet processing software. Supporting the most advanced MIPS processors,
the Marvell Horizon MV96340 communications controller presents the most complete solution available today
for implementing next-generation, high-performance, scalable, and affordable architectures for a large variety
of converged, secured and end-to-end Quality of Service (QoS) applications.
64-Bit 125 MHz (SysAD)
NetGX陋
DDR
CPU Interface
64-Bit @ 125 MHz
Co-Processor
SDRAM
8 Ports of 55 Mbps
MPSC7
Device
32-Bit @ 125 MHz
Bus
MPSC6
MPSC5
4 Ports of
Crossbar Fabric
IDMA
MPSC4
(MV64340)
MPSC3
GPIO
MPSC2
MPSC1
TWSI
MPSC0
10/100/1000 10/100/1000 PCI-(X)
PCI-(X)
MAC
MAC
32-Bit
32-Bit
66/133 MHz 66/133 MHz
PRODUCT OVERVIEW
Fig 1. Horizon陋 Communications Controllers (MV96340) Block Diagram
FEATURES
樓
Internal X-bar interconnect fabric
脨 High throughput, fully concurrent and non-blocking architecture
樓
64-bit MIPS CPU bus interface
脨 125 MHz SysAD LVCMOS and HSTL bus modes
樓
High-performance 64-bit DDR SDRAM controller
脨 133 MHz ECC protected memory interface
脨 8 GB address space
脨 4-way bank interleaving and 16 open pages
樓
32-bit device controller
脨 Five chip selects with programmable timing, interfacing a broad
range of synchronous and asynchronous devices
樓
High-performance PCI 2.2/66 MHz or PCI-X 1.0/133 MHz interfaces
脨 Dual 32-bit or single 64-bit con脼gurable
脨 Programmable PCI bus arbiters
樓
Two 10/100/1000 Mbps Gigabit Ethernet (GbE) MACs
脨 MII and RGMII interfaces
脨 Eight entry priority queuing on receive and transmit
脨 TCP/UDP/IP hardware checksum on receive and transmit
BENEFITS
樓
Allows overall system performance optimization and
full throughputs utilization
樓
Supports all 64-bit MIPS processors, allowing customers to choose
the right performance and cost solution for their architecture
樓
Supports the industry-standard DDR SDRAM, allowing customers
to easily migrate from existing SDR SDRAM solutions and resolve
memory bottlenecks
樓
Simple and versatile local bus to support a wide range of
peripheral devices
樓
Allow customer to use readily available PCI-based ASICs and
off-the-shelf solutions to fully utilize the interface performance
樓
Combined with Marvell Alaska
簍
PHYs, customers can migrate from
10/100 ports to emerging Gigabit interfaces
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