TMOS E-FET.
鈩?/div>
Power Field Effect Transistor
D3PAK for Surface Mount
Designer's
MTV20N50E
TMOS POWER FET
20 AMPERES
500 VOLTS
RDS(on) = 0.240 OHM
N鈥揅hannel Enhancement鈥揗ode Silicon Gate
The D3PAK package has the capability of housing the largest chip
size of any standard, plastic, surface mount power semiconductor.
This allows it to be used in applications that require surface mount
components with higher power and lower RDS(on) capabilities. This
high voltage MOSFET uses an advanced termination scheme to
provide enhanced voltage鈥揵locking capability without degrading
performance over time. In addition, this advanced TMOS E鈥揊ET is
designed to withstand high energy in the avalanche and commuta-
tion modes. The new energy efficient design also offers a drain鈥搕o鈥?/div>
source diode with a fast recovery time. Designed for high voltage,
high speed switching applications in surface mount PWM motor
controls and both ac鈥揹c and dc鈥揹c power supplies. These devices
are particularly well suited for bridge circuits where diode speed and
commutating safe operating areas are critical and offer additional
safety margin against unexpected voltage transients.
廬
D
N鈥揅hannel
G
CASE 433鈥?1, Style 2
D3PAK Surface Mount
鈥?/div>
Robust High Voltage Termination
S
鈥?/div>
Avalanche Energy Specified
鈥?/div>
Source鈥搕o鈥揇rain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
鈥?/div>
Diode is Characterized for Use in Bridge Circuits
鈥?/div>
IDSS and VDS(on) Specified at Elevated Temperature
鈥?/div>
Short Heatsink Tab Manufactured 鈥?Not Sheared
鈥?/div>
Specifically Designed Leadframe for Maximum Power Dissipation
鈥?/div>
Available in 24 mm, 13鈥搃nch/500 Unit Tape & Reel, Add 鈥揜L Suffix to Part Number
MAXIMUM RATINGS
(TC = 25擄C unless otherwise noted)
Rating
Drain鈥搕o鈥揝ource Voltage
Drain鈥搕o鈥揋ate Voltage (RGS = 1.0 M鈩?
Gate鈥搕o鈥揝ource Voltage 鈥?Continuous
Gate鈥搕o鈥揝ource Voltage
鈥?Non鈥揜epetitive (tp
鈮?/div>
10 ms)
Drain Current 鈥?Continuous
Drain Current
鈥?Continuous @ 100擄C
Drain Current
鈥?Single Pulse (tp
鈮?/div>
10
碌s)
Total Power Dissipation
Derate above 25擄C
Total Power Dissipation @ TC = 25擄C (1)
Operating and Storage Temperature Range
Single Pulse Drain鈥搕o鈥揝ource Avalanche Energy 鈥?Starting TJ = 25擄C
(VDD = 100 Vdc, VGS = 10 Vdc, Peak IL = 20 Apk, L = 10 mH, RG = 25
鈩?/div>
)
Thermal Resistance 鈥?Junction to Case
Thermal Resistance
鈥?Junction to Ambient
Thermal Resistance
鈥?Junction to Ambient (1)
Maximum Lead Temperature for Soldering Purposes, 1/8鈥?from case for 10 seconds
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
Symbol
VDSS
VDGR
VGS
ID
ID
IDM
PD
Value
500
500
鹵20
鹵40
20
14.1
60
250
2.0
3.57
鈥?55 to 150
2000
Unit
Vdc
Vdc
Vdc
Adc
Apk
Watts
W/擄C
Watts
擄C
mJ
TJ, Tstg
EAS
R
胃JC
R
胃JA
R
胃JA
TL
0.5
62.5
35
260
擄C/W
擄C
Designer鈥檚 Data for 鈥淲orst Case鈥?Conditions
鈥?The Designer鈥檚 Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves 鈥?representing boundaries on device characteristics 鈥?are given to facilitate 鈥渨orst case鈥?design.
E鈥揊ET and Designer鈥檚 are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
漏
Motorola TMOS
Motorola, Inc. 1996
Power MOSFET Transistor Device Data
1
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