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MTL005 Datasheet

  • MTL005

  • XGA Flat Panel Controller

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  • ETC

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MYSON
TECHNOLOGY
MTL005
Rev 0.9
XGA Flat Panel Controller
FEATURES
General
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Auto configuration of sampling clock frequency, phase, H/V center, as well as white balance.
Auto detection of present or non-present or over range sync signals and their polarities.
Composite sync separation and odd/even field detection of interlaced video.
No external memory required.
On-chip output PLL provide clock frequency fine-tune (inverse, duty cycle and delay).
Serial 2-wire I
2
C host interface.
3.3V supplier, 5V I/O tolerance in 128-pin PQFP package.
Single RGB (24-bit) input rates up to 100MHz.
Support both non-interlaced and interlaced RGB graphic input signals.
YUV 4:2:2 or YUV 4:1:1 (CCIR601/CCIR656) interlaced video input.
Glue-free connection to Philips SAA711x digital video decoder.
Built-in YUV to RGB color space converter.
Compliant with digital LVDS/PanelLink TMDS input interface.
PC input resolution up to XGA 1024x768 @85Hz.
Independent programmable Horizontal and Vertical scaling up ratios from 1 to 32
Flexible de-interlacing unit for digital YUV video input data.
Zoom to full screen resolution of de-interlaced YUV video data stream.
Built-in programmable gain control for white balance alignments.
Built-in programmable 8-bit gamma correction table.
Built-in programmable temporal color dithering.
Built-in programmable interpolation look-up table.
Support smooth panning under viewing window change.
Single pixel (18/24-bit) or Dual pixel (36/48-bit) per clock digital RGB output.
Built-in output timing generator with programmable clock and H/V sync.
Support VGA/SVGA/XGA display resolution.
Overlay input interface with external OSD controller.
Double scan capability for interlaced input.
Input Processor
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Video Processor
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Output Processor
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GENERAL DESCRIPTION
The MTL005 Flat Panel Display (FPD) Controller is a low-cost input format converter for TFT-LCD Monitor or
LCD TV application which accepts 15-pin D-sub RGB graphic signals (through ADC), YUV signals from
digital video decoder or digital RGB graphic signals from PanelLink TMDS receiver. It comprises a RGB/YUV
input processor, video scaling up processor, OSD input interface and output display processor in 128-pin
PQFP.
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without
notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
Revision 0.9
-
1
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2000/12/29

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