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MTL003 Datasheet

  • MTL003

  • SXGA Flat Panel Controller

  • 64頁

  • ETC

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MYSON
TECHNOLOGY
MTL003
(Rev. 0.95)
SXGA Flat Panel Controller
FEATURES
General
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Auto configuration of sampling clock frequency, phase, H/V center, as well as white balance.
Auto detection of present or non-present or over range sync signals and their polarities.
Composite sync separation and odd/even field detection of interlaced video.
On-chip output PLL provide clock frequency fine-tune (inverse, duty cycle and delay).
Selection of serial 2-wire I
2
C or 8-bit direct host interface to 8-bit MCU.
3.3V supplier, 5V I/O tolerance in 256-pin PQFP or 272-pin BGA package.
Single RGB (24-bit) or Dual RGB (48-bit) input rates up to 160MHz.
Support both non-interlaced and interlaced RGB graphic input signals.
YUV 4:2:2 or YUV 4:1:1 (CCIR601) interlaced video input.
Glue-less connection to Philips SAA711x digital video decoder.
Built-in YUV to RGB color space converter.
Compliant with digital LVDS/PanelLink TMDS input interface.
PC input resolution up to SXGA 1280x1024 @85Hz.
Independent programmable Horizontal and Vertical scaling ratios from 1/32 to 32
Flexible de-interlacing unit for digital YUV video input data.
Zoom to full screen resolution of de-interlaced YUV video data stream.
Built-in programmable gain control for white balance alignments.
Built-in programmable 8-bit or 10-bit gamma correction table.
Built-in programmable temporal color dithering.
Built-in programmable interpolation look-up table.
Support smooth panning under viewing window change.
Single pixel (18/24-bit) or Dual pixel (36/48-bit) per clock digital RGB output.
Built-in output timing generator with programmable clock and H/V sync.
Support VGA/SVGA/XGA/SXGA display resolution.
Overlay input interface with external OSD controller.
Double scan capability for interlaced input.
Support 48/32/24 bit bus width, SDRAM/SGRAM x2 or x3 configuration.
Optional display through internal line buffer without external frame-buffer memory.
Support power down mode.
Input Processor
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Video Processor
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Output Processor
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Memory Interface
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GENERAL DESCRIPTION
The MTL003 Flat Panel Display (FPD) Controller is an input format converter for TFT-LCD Monitor or LCD
TV application which accepts 15-pin D-sub RGB graphic signals (through ADC), YUV signals from digital
video decoder or digital RGB graphic signals from PanelLink TMDS receiver. It includes a RGB/YUV input
processor, configurable frame-buffer memory interface, video scaling up/down processor, OSD input
interface and output display processor in 256-pin PQFP or 272-pin BGA package.
Revision 0.95
-1-
2000/06/14

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