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MTD2N40E Datasheet

  • MTD2N40E

  • TMOS POWER FET 2.0 AMPERES 400 VOLTS RDS(on) = 3.5 OHM

  • 10頁

  • MOTOROLA   MOTOROLA

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MTD2N40E/D
鈩?/div>
Data Sheet
TMOS E-FET.
鈩?/div>
High Energy Power FET
DPAK for Surface Mount
Designer's
MTD2N40E
Motorola Preferred Device
N鈥揅hannel Enhancement鈥揗ode Silicon Gate
This advanced high voltage TMOS E鈥揊ET is designed to
withstand high energy in the avalanche and switch efficiently. This
new high energy device also offers a drain鈥搕o鈥搒oure diode with fast
recovery time. Designed for high voltage, high speed switching
applications such as power supplies, PWM motor controls and
other inductive loads, the avalanche energy capability is specified
to eliminate the guesswork in designs where inductive loads are
switched and offer additional safety margin against unexpected
voltage transients.
鈥?/div>
Robust High Voltage Termination
鈥?/div>
Avalanche Energy Specified
鈥?/div>
Source鈥搕o鈥揇rain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
鈥?/div>
Diode is Characterized for Use in Bridge Circuits
鈥?/div>
IDSS and VDS(on) Specified at Elevated Temperature
鈥?/div>
Surface Mount Package Available in 16 mm, 13鈥搃nch/2500
Unit Tape & Reel, Add 鈥揟4 Suffix to Part Number
鈥?/div>
Replaces MTD1N40E
MAXIMUM RATINGS
(TC = 25擄C unless otherwise noted)
Rating
Drain鈥揝ource Voltage
Drain鈥揋ate Voltage (RGS = 1.0 M鈩?
Gate鈥揝ource Voltage 鈥?Continuous
Gate鈥揝ource Voltage
鈥?Non鈥揜epetitive (tp
鈮?/div>
10 ms)
Drain Current 鈥?Continuous @ TC = 25擄C
Drain Current
鈥?Continuous @ 100擄C
Drain Current
鈥?Single Pulse (tp
鈮?/div>
10
碌s)
Total Power Dissipation @ TC = 25擄C
Derate above 25擄C
Total Power Dissipation @ TC = 25擄C, when mounted to minimum recommended pad size
Operating and Storage Temperature Range
Single Pulse Drain鈥搕o鈥揝ource Avalanche Energy 鈥?Starting TJ = 25擄C
(VDD = 100 Vdc, VGS = 10 Vdc, IL = 3.0 Apk, L = 10 mH, RG = 25
鈩?
Thermal Resistance 鈥?Junction to Case
Thermal Resistance
鈥?Junction to Ambient
Thermal Resistance
鈥?Junction to Ambient, when mounted to minimum recommended pad size
Maximum Temperature for Soldering Purposes, 1/8鈥?from case for 10 seconds
Symbol
VDSS
VDGR
VGS
VGSM
ID
ID
IDM
PD
D
TMOS POWER FET
2.0 AMPERES
400 VOLTS
RDS(on) = 3.5 OHM
廬
CASE 369A鈥?3, Style 2
DPAK
G
S
Value
400
400
鹵
20
鹵
40
2.0
1.5
6.0
40
0.32
1.75
鈥?55 to 150
45
3.13
100
71.4
260
Unit
Vdc
Vdc
Vdc
Vpk
Adc
Apk
Watts
W/擄C
Watts
擄C
mJ
擄C/W
TJ, Tstg
EAS
R
胃JC
R
胃JA
R
胃JA
TL
擄C
Designer鈥檚 Data for 鈥淲orst Case鈥?Conditions
鈥?The Designer鈥檚 Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves 鈥?representing boundaries on device characteristics 鈥?are given to facilitate 鈥渨orst case鈥?design.
E鈥揊ET and Designer鈥檚 are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred
devices are Motorola recommended choices for future use and best overall value.
漏
Motorola TMOS
Motorola, Inc. 1995
Power MOSFET Transistor Device Data
1

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