TMOS E-FET.
鈩?/div>
High Energy Power FET
D2PAK for Surface Mount
Designer's
MTB8N50E
TMOS POWER FET
8.0 AMPERES
500 VOLTS
RDS(on) = 0.8 OHM
N鈥揅hannel Enhancement鈥揗ode Silicon Gate
The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower RDS(on) capabilities. This high voltage
MOSFET uses an advanced termination scheme to provide
enhanced voltage鈥揵locking capability without degrading perfor-
mance over time. In addition, this advanced TMOS E鈥揊ET is
designed to withstand high energy in the avalanche and commuta-
tion modes. This new energy efficient design also offers a
drain鈥搕o鈥搒ource diode with a fast recovery time. Designed for low
voltage, high speed switching applications in power supplies,
converters, PWM motor controls, these devices are particularly well
suited for bridge circuits where diode speed and commutating safe
operating areas are critical and offer additional safety margin
against unexpected voltage transients.
廬
D
G
S
CASE 418B鈥?2, Style 2
D2PAK
鈥?/div>
Robust High Voltage Termination
鈥?/div>
Avalanche Energy Specified
鈥?/div>
Source鈥搕o鈥揇rain Diode Recovery Time Comparable
to a Discrete Fast Recovery Diode
鈥?/div>
Diode is Characterized for Use in Bridge Circuits
鈥?/div>
IDSS and VDS(on) Specified at Elevated Temperature
鈥?/div>
Short Heatsink Tab Manufactured 鈥?Not Sheared
鈥?/div>
Specifically Designed Leadframe for Maximum Power Dissipation
鈥?/div>
Available in 24 mm 13鈥搃nch/800 Unit Tape & Reel, Add T4 Suffix to Part Number
MAXIMUM RATINGS
(TJ = 25擄C unless otherwise noted)
Rating
Drain鈥搕o鈥揝ource Voltage
Drain鈥搕o鈥揋ate Voltage (RGS = 1.0 M
W
)
Gate鈥搕o鈥揝ource Voltage 鈥?Continuous
Gate鈥搕o鈥揝ource Voltage
鈥?Non鈥搑epetitive (tp
鈮?/div>
10 ms)
Drain Current 鈥?Continuous @ TC = 25擄C
Drain Current
鈥?Continuous @ TC = 100擄C
Drain Current
鈥?Single Pulse (tp
鈮?/div>
10
m
s)
Total Power Dissipation @ TC = 25擄C
Derate above 25擄C
Operating and Storage Temperature Range
Single Pulse Drain鈥搕o鈥揝ource Avalanche Energy 鈥?STARTING TJ = 25擄C
(VDD = 25 Vdc, VGS = 10 Vdc, PEAK IL = 8.0 Apk, L = 16 mH, RG = 25
W
)
Thermal Resistance
鈥?Junction鈥搕o鈥揅ase
鈥?Junction鈥搕o鈥揂mbient
鈥?Junction鈥搕o鈥揂mbient (1)
Maximum Lead Temperature for Soldering Purposes, 1/8鈥?from Case for 5 sec.
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
Symbol
VDSS
VDGR
VGS
VGSM
ID
ID
IDM
PD
TJ, Tstg
EAS
Value
500
500
鹵20
鹵40
8.0
5.0
32
125
1.0
鈥?55 to 150
510
Unit
Vdc
Vdc
Vdc
Vpk
Adc
Apk
Watts
W/擄C
擄C
mJ
R
q
JC
R
q
JA
R
q
JA
TL
1.0
62.5
50
260
擄C/W
擄C
This document contains information on a new product. Specifications and information herein are subject to change without notice.
E鈥揊ET and Designer鈥檚 are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
REV 1
漏
Motorola TMOS
Motorola, Inc. 1996
Power MOSFET Transistor Device Data
1
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TMOS POWER FET 8.0 AMPERES 500 VOLTS
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TMOS POWER FET 8.0 AMPERES 500 VOLTS
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TMOS POWER FET 8.0 AMPERES 500 VOLTS
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