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MTB50P03HDL Datasheet

  • MTB50P03HDL

  • TMOS POWER FET LOGIC LEVEL 50 AMPERES 30 VOLTS

  • 12頁(yè)

  • MOTOROLA   MOTOROLA

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MTB50P03HDL/D
鈩?/div>
Data Sheet
HDTMOS E-FET.
鈩?/div>
High Energy Power FET
D2PAK for Surface Mount
Designer's
MTB50P03HDL
Motorola Preferred Device
P鈥揅hannel Enhancement鈥揗ode Silicon Gate
The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower RDS(on) capabilities. This advanced
high鈥揷ell density HDTMOS power FET is designed to withstand
high energy in the avalanche and commutation modes. This new
energy efficient design also offers a drain鈥搕o鈥搒ource diode with a
fast recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
鈥?/div>
Avalanche Energy Specified
鈥?/div>
Source鈥搕o鈥揇rain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
鈥?/div>
Diode is Characterized for Use in Bridge Circuits
鈥?/div>
IDSS and VDS(on) Specified at Elevated Temperature
鈥?/div>
Short Heatsink Tab Manufactured 鈥?Not Sheared
鈥?/div>
Specially Designed Leadframe for Maximum Power Dissipation
鈥?/div>
Available in 24 mm 13鈥搃nch/800 Unit Tape & Reel, Add T4
Suffix to Part Number
MAXIMUM RATINGS
(TC = 25擄C unless otherwise noted)
Rating
Drain鈥揝ource Voltage
Drain鈥揋ate Voltage (RGS = 1.0 M鈩?
Gate鈥揝ource Voltage 鈥?Continuous
Gate鈥揝ource Voltage
鈥?Non鈥揜epetitive (tp
鈮?/div>
10 ms)
Drain Current 鈥?Continuous
Drain Current
鈥?Continuous @ 100擄C
Drain Current
鈥?Single Pulse (tp
鈮?/div>
10
碌s)
Total Power Dissipation
Derate above 25擄C
Total Power Dissipation @ TC = 25擄C, when mounted with the minimum recommended pad size
Operating and Storage Temperature Range
Single Pulse Drain鈥搕o鈥揝ource Avalanche Energy 鈥?Starting TJ = 25擄C
(VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 50 Apk, L = 1.0 mH, RG = 25
鈩?
Thermal Resistance 鈥?Junction to Case
Thermal Resistance
鈥?Junction to Ambient
Thermal Resistance
鈥?Junction to Ambient, when mounted with the minimum recommended pad size
Maximum Lead Temperature for Soldering Purposes, 1/8鈥?from case for 10 seconds
G
TMOS POWER FET
LOGIC LEVEL
50 AMPERES
30 VOLTS
RDS(on) = 0.025 OHM
鈩?/div>
D
CASE 418B鈥?3, Style 2
D2PAK
S
Symbol
VDSS
VDGR
VGS
VGSM
ID
ID
IDM
PD
Value
30
30
鹵15
鹵
20
50
31
150
125
1.0
2.5
鈥?55 to 150
1250
1.0
62.5
50
260
Unit
Vdc
Vdc
Vdc
Vpk
Adc
Apk
Watts
W/擄C
Watts
擄C
mJ
擄C/W
TJ, Tstg
EAS
R
胃JC
R
胃JA
R
胃JA
TL
擄C
Designer鈥檚 Data for 鈥淲orst Case鈥?Conditions
鈥?The Designer鈥檚 Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves 鈥?representing boundaries on device characteristics 鈥?are given to facilitate 鈥渨orst case鈥?design.
Designer鈥檚, E鈥揊ET, and HDTMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred
devices are Motorola recommended choices for future use and best overall value.
REV 2
Motorola TMOS
漏
Motorola, Inc. 1997
Power MOSFET Transistor Device Data
1

MTB50P03HDL 產(chǎn)品屬性

  • ON Semiconductor

  • MOSFET

  • P-Channel

  • - 30 V

  • +/- 15 V

  • 50 A

  • 0.025 Ohms

  • Single

  • + 150 C

  • SMD/SMT

  • D2PAK

  • Tube

  • 218 ns

  • 20 S

  • - 55 C

  • 125 W

  • 340 ns

  • 50

  • 90 ns

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