TMOS E-FET.
鈩?/div>
High Energy Power FET
D2PAK for Surface Mount
Designer's
MTB16N25E
Motorola Preferred Device
N鈥揅hannel Enhancement鈥揗ode Silicon Gate
The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower RDS(on) capabilities. This advanced
TMOS E鈥揊ET is designed to withstand high energy in the
avalanche and commutation modes. The new energy efficient
design also offers a drain鈥搕o鈥搒ource diode with a fast recovery
time. Designed for low voltage, high speed switching applications in
power supplies, converters and PWM motor controls, these
devices are particularly well suited for bridge circuits where diode
speed and commutating safe operating areas are critical and offer
additional safety margin against unexpected voltage transients.
鈥?/div>
Avalanche Energy Specified
鈥?/div>
Source鈥搕o鈥揇rain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
鈥?/div>
Diode is Characterized for Use in Bridge Circuits
鈥?/div>
IDSS and VDS(on) Specified at Elevated Temperature
鈥?/div>
Short Heatsink Tab Manufactured 鈥?Not Sheared
鈥?/div>
Specially Designed Leadframe for Maximum Power Dissipation
鈥?/div>
Available in 24 mm 13鈥搃nch/800 Unit Tape & Reel, Add 鈥揟4
Suffix to Part Number
G
S
TMOS POWER FET
16 AMPERES
250 VOLTS
RDS(on) = 0.25 OHM
廬
D
CASE 418B鈥?2, Style 2
D2PAK
MAXIMUM RATINGS
(TC = 25擄C unless otherwise noted)
Rating
Drain鈥揝ource Voltage
Drain鈥揋ate Voltage (RGS = 1.0 M鈩?
Gate鈥揝ource Voltage 鈥?Continuous
Gate鈥揝ource Voltage
鈥?Non鈥揜epetitive (tp
鈮?/div>
10 ms)
Drain Current 鈥?Continuous
Drain Current
鈥?Continuous @ TC = 100擄C
Drain Current
鈥?Single Pulse (tp
鈮?/div>
10
碌s)
Total Power Dissipation @ TC = 25擄C
Derate above 25擄C
Total Power Dissipation @ TA = 25擄C, when mounted with the minimum recommended pad size
Operating and Storage Temperature Range
Single Pulse Drain鈥搕o鈥揝ource Avalanche Energy 鈥?Starting TJ = 25擄C
(VDD = 80 Vdc, VGS = 10 Vdc, IL = 16 Apk, L = 3.0 mH, RG = 25
鈩?/div>
)
Thermal Resistance 鈥?Junction to Case
Thermal Resistance
鈥?Junction to Ambient
Thermal Resistance
鈥?Junction to Ambient, when mounted with the minimum recommended pad size
Maximum Lead Temperature for Soldering Purposes, 1/8鈥?from case for 10 seconds
Symbol
VDSS
VDGR
VGS
VGSM
ID
ID
IDM
PD
Value
250
250
鹵
20
鹵
40
16
10
56
125
1.0
2.5
鈥?55 to 150
384
1.0
62.5
50
260
Unit
Vdc
Vdc
Vdc
Vpk
Adc
Apk
Watts
W/擄C
Watts
擄C
mJ
擄C/W
TJ, Tstg
EAS
R
胃JC
R
胃JA
R
胃JA
TL
擄C
Designer鈥檚 Data for 鈥淲orst Case鈥?Conditions
鈥?The Designer鈥檚 Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves 鈥?representing boundaries on device characteristics 鈥?are given to facilitate 鈥渨orst case鈥?design.
E鈥揊ET and Designer鈥檚 are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred
devices are Motorola recommended choices for future use and best overall value.
漏
Motorola TMOS
Motorola, Inc. 1995
Power MOSFET Transistor Device Data
1
MTB16N25E相關(guān)型號PDF文件下載
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