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MT9VDDT1672A Datasheet

  • MT9VDDT1672A

  • DDR SDRAM DIMM

  • 29頁(yè)

  • MICRON

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128MB, 256MB (x72, ECC)
184-Pin DDR SDRAM DIMM
DDR SDRAM
DIMM
Features
鈥?JEDEC-standard 184-pin dual in-line memory
module (DIMM)
鈥?Fast data transfer rates PC1600, PC2100, or PC2700
鈥?Utilizes 200 MT/s, 266 MT/s, and 333MT/s DDR
SDRAM components
鈥?ECC-optimized pinout 128MB (16 Meg x 72), 256MB
(32 Meg x 72)
鈥?V
DD
= V
DD
Q= +2.5V
鈥?V
DDSPD
= +2.3V to +3.6V
鈥?+2.5V I/O (SSTL_2 compatible)
鈥?Commands entered on each positive CK edge
鈥?DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
鈥?Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
鈥?Bidirectional data strobe (DQS) transmitted/
received with data鈥攊.e., source-synchronous data
capture
鈥?Differential clock inputs (CK and CK#)
鈥?Four internal device banks for concurrent operation
鈥?Programmable burst lengths: 2, 4, or 8
鈥?Auto precharge option
鈥?Auto Refresh and Self Refresh Modes
鈥?15.6碌s (128MB), 7.8125碌s (256MB) maximum
average periodic refresh interval
鈥?Serial Presence-Detect (SPD) with EEPROM
鈥?Programmable READ CAS latency
MT9VDDT1672A - 128MB
MT9VDDT3272A - 256MB
For the latest data sheet, please refer to the Micron
芒
Web
site:
www.micron.com/moduleds
Figure 1: 184-Pin DIMM (MO-206)
OPTIONS
鈥?Package
Unbuffered
184-pin DIMM (Gold)
184-pin DIMM (Lead-Free)
鈥?Frequency/CAS Latency
6ns, 333 MT/s (167 MHz), CL = 2.5
7.5ns, 266 MT/s (133 MHz ), CL = 2
7.5ns, 266 MT/s (133 MHz ), CL = 2
7.5ns, 266 MT/s (133 MHz ), CL = 2.5
10ns, 200 MT/s (100 MHz ), CL = 2
鈥?Self Refresh
Standard
Low Power
MARKING
A
G
Y
-335
-262
-26A
-265
-202
None
L
Table 1:
Address Table
128MB
256MB
8K
8K (A0鈥揂12)
4 (BA0, BA1)
32 Meg x 8
1K (A0鈥揂9)
1 (S0#)
4K
Refresh Count
4K (A0鈥揂11)
Row Addressing
Device Bank Addressing 4 (BA0, BA1)
16 Meg x 8
Device Configuration
1K (A0鈥揂9)
Column Addressing
1 (S0#)
Module Rank Addressing
09005aef808f8ccd
DD9C16_32X72AG_B.fm - Rev. B 2/03 EN
1
漏2003 Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

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