鈥?/div>
Time-slot interchange function between 8 pairs
of ST-BUS/GCI/MVIP streams (512 channels)
and a Parallel Data Port (PDP)
Supports star, point to point connections and
unidirectional or bidirectional ring topologies for
distributed systems
Input to Output Bypass function with minimum
delay for shared ring applications
Provides an internal latency adjustment buffer
for ring applications
Parallel port data rates up to 19.44Mbyte/s
Programmable data rates on the serial port side
(2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s)
Unidirectional Parallel switching mode for up to
2430 channels non-blocking
Per-channel direction control on the serial port
side
Per-channel message mode and high-
impedance control on both parallel and serial
port sides
8-bit multiplexed port compatible with Intel and
Motorola microcontrollers
Guarantees frame integrity when switching
wideband channels such as ISDN H0 channel
Provides external control lines allowing the fast
parallel interface to be shared with other
devices
C4OUT
C4REF1
C4REF2
FO
ISSUE 1
June 1995
鈥?/div>
Ordering Information
MT90840AK
100 Pin PQFP
MT90840AP
84 Pin PLCC
-40擄C to 85擄C
鈥?/div>
鈥?/div>
Special diagnostic alarm functions for statistical
analysis
JTAG boundary scan
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Applications
鈥?/div>
Bridging ST-BUS/MVIP buses to high speed
Time Division Multiplex backplanes at SONET
rates (STS-1/3)
High speed isochronous backbones for
distributed PBX and Local Area Network
systems
Switch platforms of up to 2430 channels with
guaranteed frame integrity for wideband
channels
Serial bus control and monitoring
Data multiplexer
High speed communications interface
Isochronous switching/multiplexing to support
IEEE 802.9 standards
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
SERIAL PORT TIMING
CONTROL
PARALLEL PORT TIMING
CONTROL
PPFRo
PCKT
PPFRi
PCKR
RECEIVE PATH
DATA & CONN
MEMORIES
Serial
Data
Port
DSo[0:7]
DSi[0:7]
S-P
&
P-S
RECEIVE
LATENCY
BUFFER
PARALLEL
PORT
INTERFACE
PDi0-7
PDo0-7
Parallel
Data
Port
TCK
TMS
TDI
TDO
TRANSMIT PATH
DATA & CONN
MEMORIES
JTAG
Microprocessor Interface
EXTERNAL
CONTROL
CT0
CT1
CT2
CT3
RESET
AD[0:7] ALE
WR/ RD/ CS
R/W DS
DTACK INT
Figure 1 - Functional Block Diagram
2-189
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