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MT90710AP Datasheet

  • MT90710AP

  • High-Speed Isochronous Multiplexer

  • 12頁

  • MITEL

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廬
CMOS
MT90710
High-Speed Isochronous Multiplexer
Preliminary Information
Features
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Multiplexes eight 2.048 Mbit/s, ST-BUS links
onto one serial high-speed 20.48 Mbit/s link
15.808 Mbit/s clear bandwidth transport
Two 8 kbit/s and one 32 kbit/s oversampled
signalling channels
Embedded system timing and frame
synchronization
Frame buffer control signals generated on-chip
Check-sum generated on multiplexed frame
Remote synchronization indication
Both master and slave timing mode operation
On-chip reference generation for slave mode
synchronization
4B/5B data encoding/decoding
MT90710AP
ISSUE 1
January 1995
Ordering Information
84 Pin PLCC
0 擄C to +70 擄C
Description
The High-Speed Isochronous Multiplexer integrated
circuit multiplexes up to eight Serial Telecom
(ST-BUS) links onto a single 20 MHz loop to facilitate
point-to-point data transport requirements. The
MT90710 connects easily with standard Fiber Optic
interfaces to form a complete electric to photonic
conversion circuit. Optical transmission allows large
bandwidth inter-shelf or, in distributed systems,
inter-node communication by eliminating multiple
data buses, cable inter-connect and attendant driver
interfaces. The final result is a simple physical
interface free of the radiated emissions and
background
noise
susceptibility
problems
encountered in copper-wired environments.
Applications
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Fibre distributed sytems
Backplane concentrators
Local Area Networks (LANs)
STi0
STi5
STi6A
STi6B
STi7
DIN8K0
DIN8K1
DIN32K
STo0
STo5
STo6A
STo6B
STo7
DOUT8K0
DOUT8K1
DOUT32K
TRANSMIT
To Transmit Driver
Amplifier and Fiber
Driver Transducer
TxDATA
MODE0
MODE1
MODE2
F0b
C4b
E20i
RLED
LLED
C20o
POR
RESET
C4REFo
C4o
C40i
MUX
Overhead
Checksum
Frame Sync
4B/5B &
NRZI
Encode
PISO
Control
RECEIVE
DEMUX
Overhead
Extract &
Insert
Error Check
Frame Alignment & Buffer
External Memory Control
NRZI Decode
Sync Detect
4B/5B Decode
From Receive Pin Diode,
Pre-amp and Post-amp
Circuits
SIPO
RxDATA
Signals to
External PLL
FBDATA0
FBADDR0
FBADDR7
FBDATA7
Figure 1 - Functional Block Diagram
5-3
FBWE
FBOE

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