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MT9042AP Datasheet

  • MT9042AP

  • Global Digital Trunk Synchronizer

  • 125.77KB

  • 16頁

  • MITEL

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廬
MT9042
Global Digital Trunk Synchronizer
Preliminary Information
Features
鈥?/div>
Provides T1 and E1 clocks, and ST-BUS/GCI
framing signals locked to an input reference of
either 8 kHz (frame pulse), 1.544 MHz (T1), or
2.048 MHz (E1)
Meets AT & T TR62411 and ETSI ETS 300 011
specifications for a 1.544 MHz (T1), or
2.048 MHz (E1) input reference
Provides Time Interval Error (TIE) correction to
suppress input reference rearrangement
transients
Typical unfiltered intrinsic output jitter is
0.013 UI peak-to-peak
Jitter attenuation of 15 dB @ 10 Hz,
34 dB @ 100 Hz and 50 dB @ 5 to 40 kHz
Low power CMOS technology
ISSUE 1
June 1994
Ordering Information
MT9042AP
28 Pin PLCC
-40
擄
C to +85
擄
C
鈥?/div>
Description
The MT9042 is a digital phase-locked loop (PLL)
designed to provide timing and synchronization
signals for T1 and E1 primary rate transmission links
that are compatible with ST-BUS/GCI frame
alignment timing requirements. The PLL outputs can
be synchronized to either a 2.048 MHz, 1.544 MHz,
or 8 kHz reference. The T1 and E1 outputs are fully
compliant with AT & T TR62411 (ACCUNET
廬
T1.5)
and ETSI ETS 300 011 intrinsic jitter and jitter
transfer
specifications,
respectively,
when
synchronized to primary reference input clock rates
of either 1.544 MHz or 2.048 MHz.
The PLL also provides additional high speed output
clocks at rates of 3.088 MHz, 4.096 MHz, 8.192
MHz, and 16.384 MHz for backplane synchro-
nization.
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Applications
鈥?/div>
鈥?/div>
鈥?/div>
Synchronization and timing control for T1 and
E1 digital transmission links
ST-BUS clock and frame pulse sources
Primary Trunk Rate Converters
VDD
VSS
TRST
MCLKo
MCLKi
RST
C3
C1.5
Reference
Select
MUX
C16
TIE
Corrector
PLL
Interface
Circuit
C8
C4
C2
F0o
FP8-STB
FP8-GCI
Automatic State
Machine
Divider
PRI
SEC
RSEL
LOSS1
LOSS2
GTo
GTi
MS1
MS2
FSEL1
FSEL2
Figure 1 - Functional Block Diagram
3-97

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