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Parallel-to-serial and serial-to-parallel

conversion of up to 1536 full duplex channels or

3072 time-slots

Serial port data rates selectable between 2.048,

4.096 or 8.192 Mb/s

Provides a mechanism for a double buffer

function to be implemented in external memory

24 serial I/O lines programmable in different

modes: 12 in/12 out at 8.192 Mb/s (1536 full

duplex channels) or 24 bidirectional line modes

for 2.048 and 4.096 Mb/s

Provides a bidirectional 8-bit parallel port

operating at 16.384 or 32.768 MByte/s for direct

interface to external memory (dual port)

Provides an external 13-bit output address bus

for direct connection with an 8K-position dual

port memory

JTAG boundary scan

DS5026

ISSUE 2

August 1998

Ordering Information

MT90210AL

100 Pin PQFP

鈥?/div>

-40 to +85擄C

Description

The MT90210 is a 100-pin device used to interface a

parallel bidirectional 8 bit bus to 24 time division

multiplexed (TDM) serial streams. The device is

con鏗乬ured to perform simultaneous parallel-to-serial

and serial-to-parallel conversion with the capability

of handling up to 3072 channels, 1536 on the

transmit and 1536 on the receive direction.

Depending on the operation mode selected at the

mode pins, the individual 64 Kb/s channels on the

serial links may be con鏗乬ured as inputs or outputs.

The data on the parallel bus is in a format suitable for

interfacing with a dual-port RAM. Depending on the

data rate selected by the MD0-MD2 input pins, serial

data is clocked in and out on the serial streams at

either 2.048, 4.096 or 8.192 Mb/s.

鈥?/div>

Applications

鈥?/div>

Fast access to ST-BUS, SCSA, MVIP, and

H-MVIP serial backplanes

Voice processing cards for Computer Telephony

Integration (CTI)

Video and teleconferencing bridge cards

Fast DSP access to serial TDM buses

RDin Strobe RBC R/W1 R/W2

S0

External Memory

Access Control

Shift

Registers

Timing

Generation

Address Generator

Read

Write

Counter

Boundary

Scan Test

MUX

Mode Control

Analog

PLL

P0

鈥?/div>

P7

WBC

SCLK

HC4

C16-

C16+

F0i

PCLK

PLLVSS

LP1,LP2

PLLAGND

CKout

RST

PLLVDD

鈥?/div>

S23

TDI

TCK

TMS

TRST

TDO

Figure 1 - Functional Block Diagram

2-145

A12

A0

OEser MD2 MD1 MD0

鈥?/div>

型號(hào)

版本

描述

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MT90210AL Datasheet

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