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MT8885AP Datasheet

  • MT8885AP

  • Integrated DTMFTransceiver with Power Down & Adaptive Micro ...

  • 20頁

  • MITEL

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MT8885
廬
Integrated DTMF Transceiver
with Power Down & Adaptive
Micro Interface
Advance Information
Features
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External power down pin
Central office quality DTMF transmitter/
receiver
Low power consumption
High speed adaptive micro interface
Adjustable guard time
Automatic tone burst mode
Call progress tone detection to -30dBm
DTMF transmitter/receiver power down via
register control
ISSUE 1
May 1995
Ordering Information
MT8885AE
MT8885AN
MT8885AP
-40擄C to
24 Pin Plastic DIP
24 Pin SSOP
28 Pin PLCC
+85擄C
Applications
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Credit card systems
Paging systems
Repeater systems/mobile radio
Interconnect dialers
Personal computers
The receiver section is based upon the industry
standard MT8870 DTMF receiver while the
transmitter utilizes a switched capacitor D/A
converter for low distortion, high accuracy DTMF
signalling. Internal counters provide a burst mode
such that tone bursts can be transmitted with precise
timing. A call progress filter can be selected allowing
a microprocessor to analyze call progress tones.
The MT8885 utilizes an adaptive micro interface,
which allows the device to be connected to a number
of popular microcontrollers with minimal external
logic. The MT8885 provides enhanced power down
features.
The transmitter and receiver may
independently be powered down via register
control. A full chip power down pin provides simple
power and control capability.
Description
The MT8885 is a monolithic DTMF transceiver with
call progress filter.
It is fabricated in CMOS
technology offering low power consumption and high
reliability.
TONE
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D/A
Converters
Row and
Column
Counters
Transmit Data
Register
Status
Register
Data
Bus
Buffer
D0
D1
D2
D3
Tone Burst
Gating Cct.
IN+
IN-
GS
OSC1
OSC2
Oscillator
Circuit
Bias
Circuit
+
-
Dial
Tone
Filter
Control
Logic
Interrupt
Logic
IRQ/CP
High Group
Filter
Low Group
Filter
Control
Logic
Digital
Algorithm
and Code
Converter
Control
Register
A
Control
Register
B
I/O
Control
DS/RD
CS
R/W/WR
RS0
Steering
Logic
Receive Data
Register
V
DD
V
Ref
V
SS
PWDN
ESt
St/GT
Figure 1 - Functional Block Diagram
4-51

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