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MT58L1MY18D Datasheet

  • MT58L1MY18D

  • 16Mb SYNCBURST⑩ SRAM

  • 34頁

  • MICRON

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ADVANCE
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
16Mb SYNCBURST
鈩?/div>
SRAM
FEATURES
鈥?Fast clock and OE# access times
鈥?Single +3.3V 鹵0.165Vor 2.5V 鹵0.125V power supply
(V
DD
)
鈥?Separate +3.3V or 2.5V isolated output buffer
supply (V
DD
Q)
鈥?SNOOZE MODE for reduced-power standby
鈥?Common data inputs and data outputs
鈥?Individual BYTE WRITE control and GLOBAL
WRITE
鈥?Three chip enables for simple depth expansion and
address pipelining
鈥?Clock-controlled and registered addresses, data I/Os
and control signals
鈥?Internally self-timed WRITE cycle
鈥?Burst control (interleaved or linear burst)
鈥?Automatic power-down
鈥?100-pin TQFP package
鈥?165-pin FBGA package
鈥?Low capacitive bus loading
鈥?x18, x32, and x36 versions available
MT58L1MY18D, MT58V1MV18D,
MT58L512Y32D, MT58V512V32D,
MT58L512Y36D, MT58V512V36D
3.3V V
DD
, 3.3V or 2.5V I/O; 2.5V V
DD
, 2.5V
I/O, Pipelined, Double-Cycle Deselect
100-Pin TQFP
1
165-Pin FBGA
(Preliminary Package Data)
OPTIONS
鈥?Timing (Access/Cycle/MHz)
3.5ns/6ns/166 MHz
4.0ns/7.5ns/133 MHz
5ns/10ns/100 MHz
鈥?Configurations
3.3V V
DD
, 3.3V or 2.5V I/O
1 Meg x 18
512K x 32
512K x 36
2.5V V
DD
, 2.5V I/O
1 Meg x 18
512K x 32
512K x 36
TQFP MARKING*
-6
-7.5
-10
NOTE:
1. JEDEC-standard MS-026 BHA (LQFP).
MT58L1MY18D
MT58L512Y32D
MT58L512Y36D
MT58V1MV18D
MT58V512V32D
MT58V512V36D
T
F
None
GENERAL DESCRIPTION
The Micron
廬
SyncBurst
鈩?/div>
SRAM family employs high-
speed, low-power CMOS designs that are fabricated
using an advanced CMOS process.
Micron鈥檚 16Mb SyncBurst SRAMs integrate a 1 Meg x
18, 512K x 32, or 512K x 36 SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst
counter. All synchronous inputs pass through registers
controlled by a positive-edge-triggered single-clock in-
put (CLK). The synchronous inputs include all addresses,
all data inputs, active LOW chip enable (CE#), two
additional chip enables for easy depth expansion (CE2,
CE2#), burst control inputs (ADSC#, ADSP#, ADV#),
byte write enables (BWx#) and global write (GW#). Note
that CE2# is not available on the T Version.
Asynchronous inputs include the output enable
(OE#), clock (CLK) and snooze enable (ZZ). There is also
鈥?Packages
100-pin TQFP (3-chip enable)
165-pin FBGA
鈥?Operating Temperature Range
Commercial (0潞C to +70潞C)
*See page 34 for FBGA package marking guide.
Part Number Example:
MT58L1MY18DT-7.5
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
MT58L1MY18D_2.p65 鈥?Rev 7/00
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
漏2000, Micron Technology, Inc.

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