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MT4C16270 Datasheet

  • MT4C16270

  • DRAM 256K X 16 DRAM 5V, EDO PAGE MODE

  • 22頁

  • MICRON

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TECHNOLOGY, INC.
MT4C16270
256K x 16 DRAM
DRAM
FEATURES
鈥?Industry-standard x16 pinouts, timing, functions
and packages
鈥?High-performance CMOS silicon-gate process
鈥?Single +5V
鹵10%
power supply*
鈥?Low power, 3mW standby; 300mW active, typical
鈥?All device pins are TTL-compatible
鈥?512-cycle refresh in 8ms (9 row- and 9 column
addresses)
鈥?Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS#
(CBR) and HIDDEN
鈥?Extended Data-Out (EDO) PAGE MODE access cycle
鈥?BYTE WRITE and BYTE READ access cycles
256K x 16 DRAM
5V, EDO PAGE MODE
PIN ASSIGNMENT (Top View)
40-Pin SOJ
(DA-6)
OPTIONS
鈥?Timing
40ns access
50ns access
60ns access
鈥?Packages
Plastic SOJ (400 mil)
MARKING
-4*
-5*
-6
DJ
鈥?Part Number Example: MT4C16270DJ-4
*40ns and 50ns access specifications are limited to a V
CC
range of
鹵5%.
Contact factory for availability.
KEY TIMING PARAMETERS
SPEED
-4
-5
-6
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
CAS
t
CP
75ns
100ns
110ns
40ns
50ns
60ns
15ns
20ns
25ns
20ns
25ns
30ns
12ns
15ns
15ns
6ns
8ns
10ns
6ns
8ns
10ns
Vcc
DQ1
DQ2
DQ3
DQ4
Vcc
DQ5
DQ6
DQ7
DQ8
NC
NC
WE#
RAS#
NC
A0
A1
A2
A3
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Vss
DQ16
DQ15
DQ14
DQ13
Vss
DQ12
DQ11
DQ10
DQ9
NC
CASL#
CASH#
OE#
A8
A7
A6
A5
A4
Vss
GENERAL DESCRIPTION
The MT4C16270 is a randomly accessed solid-state
memory containing 4,194,304 bits organized in a x16 con-
figuration. The MT4C16270 has both BYTE WRITE and
WORD WRITE access cycles via two CAS# pins.
The MT4C16270 CAS# function and timing are deter-
mined by the first CAS# (CASL# or CASH#) to transition
LOW and by the last to transition back HIGH. CASL# and
CASH# function in a similar manner to CAS# in that either
MT4C16270
W06.pm5 鈥?Rev. 10/96
CASL# or CASH# will generate an internal CAS#. Use of
only one of the two results in a BYTE WRITE cycle. CASL#
transitioning LOW selects a WRITE cycle for the lower
byte (DQ1-DQ8) and CASH# transitioning LOW selects a
WRITE cycle for the upper byte (DQ9-DQ16). BYTE READ
cycles are achieved through CASL# or CASH# in the same
manner.
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
漏1996,
Micron Technology, Inc.

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