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MT49H32M9C Datasheet

  • MT49H32M9C

  • 288Mb SIO REDUCED LATENCY(RLDRAM II)

  • 44頁

  • MICRON

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16 MEG x 18, 32 MEG x 9
2.5V V
EXT
, 1.8V V
DD
, HSTL, SIO, RLDRAM II
288Mb SIO REDUCED
LATENCY (RLDRAM II)
Features
鈥?288Mb
鈥?400 MHz DDR operation (800 Mb/s/pin data rate)
鈥?Organization
鈥?16 Meg x 18, 32 Meg x 9 Separate I/O
鈥?8 banks
鈥?Cyclic bank switching for maximum bandwidth
鈥?Reduced cycle time (20ns at 400 MHz)
鈥?Nonmultiplexed addresses (address multiplexing
option available)
鈥?SRAM-type interface
鈥?Read latency (RL), row cycle time, and burst
sequence length
鈥?Balanced READ and WRITE latencies in order to
optimize data bus utilization
鈥?Data mask for WRITE commands
鈥?Differential input clocks (CK, CK#)
鈥?Differential input data clocks (DKx, DKx#)
鈥?On-chip DLL generates CK edge-aligned data and
output data clock signals
鈥?Data valid signal (QVLD)
鈥?32ms refresh (8K refresh for each bank; 64k refresh
command must be issued in total each 32ms)
鈥?144-ball FBGA package
鈥?HSTL I/O (1.5V or 1.8V nominal)
鈥?25鈩︹€?0鈩?matched impedance outputs
鈥?2.5V V
EXT
, 1.8V V
DD
, 1.5V or 1.8V V
DD
Q I/O
鈥?On-die termination (ODT) R
TT
MT49H16M18C
MT49H32M9C
Figure 1: 144-Ball FBGA
Table 1:
Valid Part Numbers
DESCRIPTION
16 Meg x 18 RLDRAM II
32 Meg x 9 RLDRAM II
PART NUMBER
MT49H16M18CFM-xx
MT49H32M9CFM-xx
Options
鈥?Clock Cycle Timing
2.5ns (400 MHz)
3.3ns (300 MHz)
5ns (200 MHz)
鈥?Configuration
16 Meg x 18
32 Meg x 9
鈥?Package
144-ball FBGA
(11mm x 18.5mm)
NOTE:
Marking
-25
-33
-5
MT49H16M18CFM
MT49H32M9CFM
FM
BM (lead-free)
1
1. Contact Micron for availability of lead-free
products.
pdf: 09005aef80a41b59/zip: 09005aef811ba111
MT49H8M18C_1.fm - Rev. F 11/04 EN
1
漏2004 Micron Technology, Inc. All rights reserved.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

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