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MT48V8M16LFFF Datasheet

  • MT48V8M16LFFF

  • SYNCHRONOUS DRAM

  • 61頁

  • MICRON

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ADVANCE
鈥?/div>
128Mb: x16, x32
MOBILE SDRAM
SYNCHRONOUS
DRAM
FEATURES
鈥?Temperature Compensated Self Refresh (TCSR)
鈥?Fully synchronous; all signals registered on positive
edge of system clock
鈥?Internal pipelined operation; column address can be
changed every clock cycle
鈥?Internal banks for hiding row access/precharge
鈥?Programmable burst lengths: 1, 2, 4, 8, or full page
鈥?Auto Precharge, includes CONCURRENT AUTO
PRECHARGE, and Auto Refresh Modes
鈥?Self Refresh Mode; standard and low power
鈥?64ms, 4,096-cycle refresh
鈥?LVTTL-compatible inputs and outputs
鈥?Low voltage power supply
鈥?Partial Array Self Refresh power-saving mode
鈥?Operating Temperature Range
Industrial (-40
o
C to +85
o
C)
MT48LC8M16LFFF, MT48V8M16LFFF 鈥?2 Meg x 16 x 4 banks
MT48LC4M32LFFC , MT48V4M32LFFC 鈥?1 Meg x 32 x 4 banks
For the latest data sheet revisions, please refer to the Micron Web
site:
www.micron.com/dramds
PIN ASSIGNMENT (Top View)
54-Ball VFBGA
1
A
B
C
D
E
F
V
SS
2
DQ15
3
V
SS
Q
4
5
6
7
V
DD
Q
8
DQ0
9
V
DD
DQ14
DQ13
V
DD
Q
V
SS
Q
DQ2
DQ1
DQ12
DQ11
V
SS
Q
V
DD
Q
DQ4
DQ3
DQ10
DQ9
V
DD
Q
V
SS
Q
DQ6
DQ5
DQ8
NC
V
SS
V
DD
LDQM
DQ7
UDQM
CLK
CKE
CAS#
RAS#
WE#
OPTIONS
鈥?V
DD
/V
DD
Q
3.3V/3.3V
2.5V/2.5V or 1.8V
鈥?Configurations
8 Meg x 16 (2 Meg x 16 x 4 banks)
4 Meg x 32 (1 Meg x 32 x 4 banks)
鈥?Package/Ball out
Plastic Package
54-ball FBGA (8mm x 9mm)(x16 only)
90-ball FBGA (11mm x 13mm)
鈥?Timing (Cycle Time)
8ns @ CL = 3 (125 MHz)
10ns @ CL = 3 (100 MHz)
Part Number Example:
MARKING
LC
V
8M16
4M32
G
H
J
NC/A12
A11
A9
BA0
BA1
CS#
A8
A7
A6
A0
A1
A10
V
SS
A5
A4
A3
A2
V
DD
Top View
(Ball Down)
FF
1
FC
1
-8
-10
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
8 Meg x 16
4 Meg x 32
2 Meg x 16 x 4 banks 1 Meg x 32 x 4 banks
4K
4K
4K (A0鈥揂11)
4K (A0鈥揂11)
4 (BA0, BA1)
4 (BA0, BA1)
512 (A0鈥揂8)
256 (A0鈥揂7)
MT48V8M16LFFC-8
NOTE:
1. See page 61 for FBGA/VFBGA Device Marking
Table.
KEY TIMING PARAMETERS
SPEED
CLOCK
ACCESS TIME
GRADE FREQUENCY CL=1* CL=2* CL=3*
-8
-10
-8
-10
-8
-10
125 MHz
100 MHz
100 MHz
83 MHz
50 MHz
40 MHz
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
19ns
22ns
鈥?/div>
鈥?/div>
8ns
8ns
鈥?/div>
鈥?/div>
7ns
7ns
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
t
RCD
t
RP
20ns
20ns
20ns
20ns
20ns
20ns
20ns
20ns
20ns
20ns
20ns
20ns
*CL = CAS (READ) latency
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 鈥?Rev. F; Pub. 9/02
鈥?/div>
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
漏2002, Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PUROPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION AND DATA SHEET SPECIFICATIONS.

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