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MT48V16M16LFFG Datasheet

  • MT48V16M16LFFG

  • MOBILE SDRAM

  • 58頁

  • MICRON

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ADVANCE
鈥?/div>
256Mb: x16
MOBILE SDRAM
MOBILE SDRAM
FEATURES
鈥?Temperature Compensated Self Refresh (TCSR)
鈥?Fully synchronous; all signals registered on
positive edge of system clock
鈥?Internal pipelined operation; column address can
be changed every clock cycle
鈥?Internal banks for hiding row access/precharge
鈥?Programmable burst lengths: 1, 2, 4, 8, or full page
鈥?Auto Precharge, includes CONCURRENT AUTO
PRECHARGE and Auto Refresh Modes
鈥?Self Refresh Mode
鈥?64ms, 8,192-cycle refresh
鈥?LVTTL-compatible inputs and outputs
鈥?Low voltage power supply
鈥?Deep Power Down
鈥?Partial Array Self Refresh power-saving mode
鈥?Industrial operating temperature (-40
o
C to +85
o
C)
MT48V16M16LFFG, MT48H16M16LFFG鈥?/div>
4 Meg x 16 x 4 banks
For the latest data sheet revisions, please refer to the Micron
Web site:
www.micron.com/dramds
PIN ASSIGNMENT (Top View)
54-Ball FBGA
1
A
B
C
D
E
F
G
H
J
V
SS
DQ14
DQ12
DQ10
DQ8
UDQM
NC/A12
A8
V
SS
2
DQ15
DQ13
DQ11
DQ9
NC
CK
A11
A7
A5
3
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
Q
V
SS
CKE
A9
A6
A4
4
5
6
7
V
DD
Q
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
CAS\
BA0
A0
A3
8
DQ0
DQ2
DQ4
DQ6
LDQM
RAS\
BA1
A1
A2
9
V
DD
DQ1
DQ3
DQ5
DQ7
WE\
CS\
A10
VDD
OPTIONS
鈥?V
DD
/V
DD
Q
2.5V/1.8V
1.8V/1.8V
鈥?Configurations
16 Meg x 16 (4 Meg x 16 x 4 banks)
鈥?WRITE Recovery (
t
WR/
t
DPL)
t
WR = 2 CLK
鈥?Plastic Packages 鈥?OCPL
1
54-ball FBGA (8mm x 14mm)
鈥?Timing (Cycle Time)
8.0ns @ CL = 3 (125MHz)
10ns @ CL = 3 (100MHz)
MARKING
V
H
16M16
FG
1
-8
-10
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
16 Meg x 16
4 Meg x 16 x 4 banks
8K
8K (A0鈥揂12)
4 (BA0, BA1)
512 (A0鈥揂8)
NOTE:
1. See page 58 for FBGA Device Marking Table.
256Mb SDRAM PART NUMBERS
PART NUMBER
MT48V16M16LFFG
MT48H16M16LFFG
ARCHITECTURE
16 Meg x 16
16 Meg x 16
VDD
2.5V
1.8V
KEY TIMING PARAMETERS
SPEED
GRADE
-8
-10
-8
-10
-8
-10
CLOCK
FREQUENCY
125 MHz
100 MHz
100 MHz
83 MHz
50 MHz
40 MHz
ACCESS TIME
CL=1* CL=2* CL=3*
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
19ns
22ns
鈥?/div>
鈥?/div>
8ns
8ns
鈥?/div>
鈥?/div>
7ns
7ns
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
SETUP HOLD
TIME TIME
2.5ns
2.5ns
2.5ns
2.5ns
2.5ns
2.5ns
1.0ns
1.0ns
1.0ns
1.0ns
1.0ns
1.0ns
*CL = CAS (READ) latency
256Mb: x16 Mobile SDRAM
MobileRamY26L_A.p65 鈥?Pub. 5/02
鈥?/div>
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
漏2002, Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PUROPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION AND DATA SHEET SPECIFICATIONS.

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