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MT48LC16M8A2 Datasheet

  • MT48LC16M8A2

  • SYNCHRONOUS DRAM

  • 1835.73KB

  • 59頁

  • MICRON

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128Mb: x4, x8, x16
SDRAM
SYNCHRONOUS
DRAM
FEATURES
鈥?PC100-, and PC133-compliant
鈥?Fully synchronous; all signals registered on positive
edge of system clock
鈥?Internal pipelined operation; column address can be
changed every clock cycle
鈥?Internal banks for hiding row access/precharge
鈥?Programmable burst lengths: 1, 2, 4, 8, or full page
鈥?Auto Precharge, includes CONCURRENT AUTO
PRECHARGE, and Auto Refresh Modes
鈥?Self Refresh Mode; standard and low power
鈥?64ms, 4,096-cycle refresh
鈥?LVTTL-compatible inputs and outputs
鈥?Single +3.3V 鹵0.3V power supply
MT48LC32M4A2 鈥?8 Meg x 4 x 4 banks
MT48LC16M8A2 鈥?4 Meg x 8 x 4 banks
MT48LC8M16A2 鈥?2 Meg x 16 x 4 banks
For the latest data sheet, please refer to the Micron Web
site:
www.micron.com/dramds
PIN ASSIGNMENT (Top View)
54-Pin TSOP
x4 x8 x16
-
-
NC
DQ0
NC
DQ0
V
DD
DQ0
-
V
DD
Q
NC
DQ1
DQ1 DQ2
-
VssQ
NC
DQ3
DQ2 DQ4
-
V
DD
Q
NC
DQ5
DQ3 DQ6
-
VssQ
NC
DQ7
V
DD
-
NC DQML
-
WE#
-
CAS#
-
RAS#
CS#
-
BA0
-
BA1
-
A10
-
A0
-
A1
-
A2
-
A3
-
V
DD
-
x16 x8 x4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
-
-
NC
NC
-
NC
DQ1
-
OPTIONS
鈥?Configurations
32 Meg x 4 (8 Meg x 4 x 4 banks)
16 Meg x 8 (4 Meg x 8 x 4 banks)
8 Meg x 16 (2 Meg x 16 x 4 banks)
鈥?WRITE Recovery (
t
WR)
t
WR = 鈥? CLK鈥?/div>
1
鈥?Package/Pinout
Plastic Package 鈥?OCPL
2
54-pin TSOP II (400 mil)
60-ball FBGA (8mm x 16mm)
60-ball FBGA (11mm x 13mm)
鈥?Timing (Cycle Time)
10ns @ CL = 2 (PC100)
7.5ns @ CL = 3 (PC133)
7.5ns @ CL = 2 (PC133)
鈥?Self Refresh
Standard
Low power
鈥?Operating Temperature Range
Commercial (0
o
C to +70
o
C)
Industrial (-40
o
C to +85
o
C)
Part Number Example:
MARKING
32M4
16M8
8M16
A2
NC
-
NC
TG
FB
3,6
FC
3,6
-8E
3,4,5
-75
-7E
None
L
None
IT
3
-
-
-
-
-
-
-
-
-
-
-
-
-
Vss
DQ15 DQ7
VssQ
-
DQ14
NC
DQ13 DQ6
V
DD
Q
-
DQ12
NC
DQ11 DQ5
VssQ
-
DQ10
NC
DQ9 DQ4
V
DD
Q
-
DQ8
NC
-
Vss
-
NC
DQMH DQM
-
CLK
-
CKE
NC
-
A11
-
A9
-
A8
-
A7
-
A6
-
A5
-
A4
-
Vss
-
-
NC
-
NC
DQ3
-
NC
NC
-
NC
DQ2
-
NC
-
-
DQM
-
-
-
-
-
-
-
-
-
-
-
Note:
The # symbol indicates signal is active LOW. A dash (鈥?
indicates x8 and x4 pin function is same as x16 pin function.
32 Meg x 4
16 Meg x 8
8 Meg x 16
8 Meg x 4 x 4 banks 4 Meg x 8 x 4 banks 2 Meg x 16 x 4 banks
4K
4K
4K
4K (A0鈥揂11)
4 (BA0, BA1)
2K (A0鈥揂9, A11)
4K (A0鈥揂11)
4 (BA0, BA1)
1K (A0鈥揂9)
4K (A0鈥揂11)
4 (BA0, BA1)
512 (A0鈥揂8)
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
KEY TIMING PARAMETERS
SPEED
GRADE
-7E
-7E
-75
-8E
3,4,5
-75
-8E
3 ,4,5
CLOCK
ACCESS TIME SETUP
FREQUENCY CL = 2* CL = 3* TIME
143 MHz
133 MHz
133 MHz
125 MHz
100 MHz
100 MHz
鈥?/div>
5.4ns
鈥?/div>
鈥?/div>
6ns
6ns
5.4ns
鈥?/div>
5.4ns
6ns
鈥?/div>
鈥?/div>
1.5ns
1.5ns
1.5ns
2ns
1.5ns
2ns
HOLD
TIME
0.8ns
0.8ns
0.8ns
1ns
0.8ns
1ns
MT48LC16M8A2TG-7E
NOTE:
1.
2.
3.
4.
5.
6.
Refer to Micron Technical Note: TN-48-05.
Off-center parting line.
Consult Micron for availability.
Not recommended for new designs.
Shown for PC100 compatability.
See page 59 for FBGA Device Marking Table.
*CL = CAS (READ) latency
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 鈥?Rev. E; Pub. 1/02
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
漏2001, Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

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