128Mb: x16 鈥?Mobile SDRAM
Features
Synchronous DRAM
MT48H8M16LF - 2 Meg x 16 x 4 banks
Features
鈥?Temperature compensated self refresh (TCSR)
鈥?Fully synchronous; all signals registered on positive
edge of system clock
鈥?Internal pipelined operation; column address can
be changed every clock cycle
鈥?Internal banks for hiding row access/precharge
鈥?Programmable burst lengths: 1, 2, 4, 8, or full page
鈥?Auto precharge, includes concurrent auto
precharge, and auto refresh modes
鈥?Self refresh mode; standard and low power
鈥?64ms, 4,096-cycle refresh
鈥?LVTTL-compatible inputs and outputs
鈥?Low voltage power supply
鈥?Partial array self refresh power-saving mode
鈥?Deep power-down mode
鈥?Programmable output drive strength
鈥?Operating temperature ranges:
Extended (-25擄C to +85擄C)
Industrial (-40擄C to +85擄C)
Figure 1: 54-Ball FBGA Assignment
(Top View)
1
A
B
C
D
E
F
G
H
J
V
SS
2
DQ15
3
V
SS
Q
4
5
6
7
V
DD
Q
8
DQ0
9
V
DD
DQ14
DQ13
V
DD
Q
V
SS
Q
DQ2
DQ1
DQ12
DQ11
V
SS
Q
V
DD
Q
DQ4
DQ3
DQ10
DQ9
V
DD
Q
V
SS
Q
DQ6
DQ5
DQ8
NC
V
SS
V
DD
LDQM
DQ7
UDQM
CLK
CKE
CAS#
RAS#
WE#
NC/A12
A11
A9
BA0
BA1
CS#
A8
A7
A6
A0
A1
A10
V
SS
A5
A4
A3
A2
V
DD
Options
鈥?V
DD
/V
DD
Q
1.8V/1.8V
鈥?Configurations
8 Meg x 16 (2 Meg x 16 x 4 banks)
鈥?Package/Ball out
54-ball FBGA, 8mm x 8mm (standard)
54-ball FBGA, 8mm x 8mm (lead-free)
鈥?Timing (Cycle Time)
8ns @ CL = 3 (125 MHz)
9.6ns @ CL = 3 (104 MHz)
鈥?Operating Temperature
Extended (-25擄C to +85擄C)
Industrial (-40擄C to +85擄C)
Marking
H
8M16
F4
B4
-8
-10
none
IT
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
Top View
(Ball Down)
Table 1:
Address Table
8 Meg x 16
2 Meg x 16 x 4 banks
4K
4K (A0鈥揂11)
4 (BA0, BA1)
512 (A0鈥揂8)
Table 2:
Key Timing Parameters
CL = CAS (READ) latency
Access Time
CL = 2
鈥?/div>
8ns
8ns
CL = 3
6ns
7ns
鈥?/div>
鈥?/div>
FBGA Part Number System
Due to space limitations, FBGA-packaged components
have an abbreviated part marking that is different from
the part number. For a quick conversion of an FBGA
code, see the FBGA Part Marking Decoder on the
Micron Web site,
www.micron.com/decoder.
PDF: 09005aef80c97087/Source: 09005aef80c97015
MT48H8M16_1.fm - Rev. E 3/05 EN
Speed
Grade
-8
-10
-8
-10
Clock
Frequency
125 MHz
104 MHz
104 MHz
83 MHz
Setup Hold
Time Time
2.5ns
2.5ns
2.5ns
2.5ns
1ns
1ns
1ns
1ns
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
漏2003 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
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