鈥?/div>
t
RAS lockout (
t
RAP =
t
RCD)
鈥?Backwards compatible with DDR200 and DDR266
MT46V32M4 鈥?8 Meg x 4 x 4 banks
MT46V16M8 鈥?4 Meg x 8 x 4 banks
MT46V8M16 鈥?2 Meg x 16 x 4 banks
For the latest data sheet revisions, please refer to the Micron
Web site:
www.micron.com/dramds
DDR333 COMPATIBILITY
DDR333 meets or surpasses all DDR266 timing re-
quirements thus assuring full backwards compatibility
with current DDR designs. In addition, these devices
support concurrent auto-precharge and
t
RAS lockout
for improved timing performance. The 128Mb, DDR333
device will support an (
t
REFI) average periodic refresh
interval of 15.6碌s.
The standard 66-pin TSOP package is offered for
point-to-point applications where the FBGA package
is intended for the multi-drop systems.
The Micron 128Mb data sheet provides full specifi-
cations and functionality unless specified herein.
CONFIGURATION
Architecture
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
32 Meg x 4
16 Meg x 8
8 Meg x 16
8 Meg x 4 x 4 banks 4 Meg x 8 x 4 banks 2 Meg x 16 x 4 banks
4K
4K (A0鈥揂11)
4 (BA0, BA1)
2K (A0鈥揂9, A11)
4K
4K (A0鈥揂11)
4 (BA0, BA1)
1K (A0鈥揂9)
4K
4K (A0鈥揂11)
4 (BA0, BA1)
512 (A0鈥?A8)
OPTIONS
PART NUMBER
32M4
16M8
8M16
TG
FJ
-6
-6T
-75Z
none
鈥?Configuration
32 Meg x 4 (8 Meg x 4 x 4 banks)
16 Meg x 8 (4 Meg x 8 x 4 banks)
8 Meg x 16 (2 Meg x 16 x 4 banks)
鈥?Plastic Package
66-Pin TSOP (OCPL)
60-Ball FBGA (16x9mm)
鈥?Timing - Cycle Time
6ns @ CL = 2.5 (DDR333B鈥揊BGA)
1
6ns @ CL = 2.5 (DDR333B鈥揟SOP)
1
7.5ns @ CL = 2 (DDR266A)
2
鈥?Self Refresh
Standard
KEY TIMING PARAMETERS
3
SPEED
GRADE
-6
-6T
-75Z
NOTE:
CLOCK RATE
CL = 2
1
DATA-OUT ACCESS DQS-DQ
1
CL = 2.5
WINDOW
2
WINDOW
2.15ns
2.0ns
2.5ns
鹵0.70ns
鹵0.75ns
鹵0.75ns
SKEW
+0.35ns
+0.45ns
+0.50ns
133 MHz
133 MHz
133 MHz
167 MHz
167 MHz
133 MHz
1. CL = CAS (Read) Latency
2. With a 50/50 clock duty cycle and a minimum clock
rate @ CL = 2 ( -75Z) and CL = 2.5 (-6, -6T).
3. Slower speeds are included in the 128Mb base data
sheet (-75, -8).
NOTE:
1. Supports PC2700 modules with 2.5-3-3 timing
2. Supports PC2100 modules with 2-3-3 timing
256Mb: x4, x8, x16 DDR333 SDRAM
128Mx4x8x16DDR333.p65 鈥?Rev. A; Pub. 10/01
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
漏2001, Micron Technology, Inc.
鈥?PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON鈥橲 PRODUCTION AND DATA SHEET SPECIFICATIONS.
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