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MT312 Datasheet

  • MT312

  • Satellite Channel Decoder

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MT312
Satellite Channel Decoder
Design Manual
Supersedes DS5347 Issue 1.2 November 2001
DM5651
ISSUE 1.2
January 2002
Key Features
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Conforms to EBU speci鏗乧ation for DVB-S and
DirecTV speci鏗乧ation for DSS.
On-chip digital 鏗乴tering supports 1 to 45MBaud
Symbol rates.
On-chip 6-bit 60 or 90MHz dual-ADC.
High speed scanning mode for blind symbol
rate/code rate acquisition.
Automatic IQ phase resolution.
No signal indicator.
Up to 鹵15MHz LNB frequency tracking.
Fully digital timing and phase recovery loops.
High level software interface for minimum
development time.
DiSEqC鈩?v2.2: receive/transmit for full control
of LNB and dish.
Ordering Information
MT312C/CG/GP1N
Applications
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DVB 1 to 45MBaud compliant satellite
receivers.
DSS 20MBaud compliant satellite receivers.
SCPC receivers. (Single Channel Per Carrier)
SMATV trans-modulators. (Single Master
Antenna TV)
LMDS (Local Multipoint Distribution Service)
Satellite PC applications.
The MT312 is a QPSK/BPSK 1 to 45MBaud
demodulator and channel decoder for digital satellite
television transmissions to the European Broadcast
Union ETS 300 421 speci鏗乧ation (ref. 1). It receives
analogue I and Q signals from the tuner, digitises
and digitally demodulates this signal, and
implements the complete DVB/DSS FEC (Forward
Error Correction), and de-scrambling function. The
output is in the form of MPEG2 or DSS transport
stream data packets. An external MPEG clock input
is provided for synchronisation to MPEG decoders
and DVB Common Interface Modules. The MT312
also provides automatic gain control to the RF front-
end devices.
The MT312 has a serial 2-wire bus interface to the
control microprocessor. Minimal software is required
to control the MT312 because of the built in
automatic search and decode control functions.
AGC control
I
Q
Low pass
Filter
I I/P
Q I/P
Channel
Decoder
MT312
Transport
stream O/P
RF I/P
AGC
AMP
SL1914
Direct
Conversion
Tuner
SL1925
Tank
2-wire bus
control
Synthesiser
SP5769
2-wire bus control
Figure 1 - System Block Diagram - SNIM5
1

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