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MT28S4M16LC Datasheet

  • MT28S4M16LC

  • SYNCFLASH MEMORY

  • 987.15KB

  • 48頁

  • MICRON

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4 MEG x 16
SYNCFLASH MEMORY
SYNCFLASH
廬
MEMORY
FEATURES
鈥?100 MHz SDRAM-compatible read timing
鈥?Fully synchronous; all signals registered on
positive edge of system clock
鈥?Internal pipelined operation; column address can
be changed every clock cycle
鈥?Internal banks for hiding row access
鈥?Programmable burst lengths: 1, 2, 4, 8, or full page
(READ)
鈥?LVTTL-compatible inputs and outputs
鈥?Single +3.3V 鹵0.3V power supply
鈥?Additional V
HH
hardware protect mode (RP#)
鈥?Four-bank architecture supports true concurrent
operations with zero latency:
Read from any bank while performing a
PROGRAM or ERASE operation to any other
bank
鈥?Deep power-down mode: 300碌A(chǔ) maximum
鈥?Cross-compatible Flash memory command set
鈥?Industry-standard, SDRAM-compatible pinouts
鈥?Pins 36 and 40 are no connects for SDRAM
MT28S4M16LC
1 Meg x 16 x 4 banks
PIN ASSIGNMENT (Top View)
54-Pin TSOP II
V
CC
DQ0
V
CC
Q
DQ1
DQ2
V
SS
Q
DQ3
DQ4
V
CC
Q
DQ5
DQ6
V
SS
Q
DQ7
V
CC
DQML
WE#
CAS#
RAS#
CS#
BA0
BA1
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
CC
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
CC
Q
DQ8
V
SS
RP#
DQMH
CLK
CKE
V
CC
P
A11
A9
A8
A7
A6
A5
A4
V
SS
OPTIONS
鈥?Configuration
4 Meg x 16 (1 Meg x 16 x 4 banks)
鈥?Read Timing (Cycle Time)
10ns (100 MHz)
12ns (83 MHz)
鈥?Package
54-pin OCPL
1
TSOP II (400 mil)
MARKING
4M16
NOTE:
The # symbol indicates signal is active LOW.
-10
-12
KEY TIMING PARAMETERS
TG
SPEED
GRADE
-10
-10
-12
-12
CLOCK
ACCESS TIME
FREQUENCY CL = 2* CL = 3*
100 MHz
66 MHz
83 MHz
66 MHz
鈥?/div>
9ns
鈥?/div>
10ns
7ns
鈥?/div>
9ns
鈥?/div>
SETUP
TIME
3ns
3ns
3ns
3ns
HOLD
TIME
2ns
2ns
2ns
2ns
鈥?Operating Temperature Range
Commercial Temperature (0潞C to +70潞C) None
NOTE:
1. Off-center parting line
Part Number Example:
MT28S4M16LCTG-10
*CL = CAS (READ) latency
GENERAL DESCRIPTION
This SyncFlash
廬
data sheet is divided into two ma-
jor sections. The SDRAM Interface Functional
Description details compatibility with the SDRAM
memory, and the Flash Memory Functional Descrip-
tion specifies the symmetrical-sectored flash architec-
ture functional commands.
4 Meg x 16 SyncFlash
MT28S4M16LC_6.p65 鈥?Rev. 6, Pub. 9/01
The MT28S4M16LC is a nonvolatile, electrically sec-
tor-erasable (Flash), programmable memory contain-
ing 67,108,864 bits organized as 4,194,304 words (16
bits). SyncFlash memory is ideal for 3.3V-only plat-
forms that require both hardware and software protec-
tion modes. Additional hardware protection modes are
1
漏2001, Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

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