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MT28F160C34 Datasheet

  • MT28F160C34

  • FLASH MEMORY

  • 28頁

  • MICRON

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ADVANCE
鈥?/div>
1 MEG x 16
3V ENHANCED+ BOOT BLOCK FLASH MEMORY
FLASH MEMORY
FEATURES
鈥?Thirty-nine erase blocks:
Eight 4K-word parameter blocks
Thirty-one 32K-word main memory blocks
鈥?V
CC
, V
CC
Q and V
PP
voltages:
3.3V 鹵5% V
CC
3.3V 鹵5% V
CC
Q
1.65V鈥?.465V and 12V V
PP
鈥?Address access times:
90ns at 3.3V 鹵5%
鈥?Low power consumption:
Standby and deep power-down mode < 1碌A(chǔ)
(typical I
CC
)
Automatic power saving feature (APS mode)
鈥?Enhanced WRITE/ERASE SUSPEND (1碌s typical)
鈥?128-bit OTP area for security purposes
鈥?Industry-standard command set compatibility
鈥?Software/hardware block protection
MT28F160C34
BALL ASSIGNMENT (Top View)
46-Ball FBGA
1
A
B
C
D
E
F
A13
2
A11
3
A8
4
V
PP
5
WP#
6
A19
7
A7
8
A4
A14
A10
WE#
RP#
A18
A17
A5
A2
A15
A12
A9
A6
A3
A1
A16
DQ14
DQ5
DQ11
DQ2
DQ8
CE#
A0
V
CC
Q
DQ15
DQ6
DQ12
DQ3
DQ9
DQ0
V
SS
OPTIONS
鈥?Timing
90ns access
鈥?Boot Block Starting Address
Top (FFFFFh)
Bottom (00000h)
鈥?Package
46-ball FBGA (6 x 8 ball grid)
鈥?Temperature Range
Extended (-40潞C to +85潞C)
Part Number Example:
NUMBER
-9
T
B
FD
ET
V
SS
DQ7
DQ13
DQ4
V
CC
DQ10
DQ1
OE#
(Ball Down)
NOTE:
See page 3 for Ball Description Table.
See last page for mechanical drawing.
MT28F160C34FD-9 TET
GENERAL DESCRIPTION
The MT28F160C34 is a nonvolatile, electrically block-
erasable (flash), programmable memory containing
16,777,216 bits organized as 1,048,576 words (16 bits).
The MT28F160C34 is manufactured on 0.22碌m process
technology in a 46-ball FBGA package.
The embedded WORD WRITE and BLOCK ERASE
functions are fully automated by an on-chip write state
machine (WSM), which simplifies these operations and
relieves the system processor of secondary tasks. The
1 Meg x 16 3V Enhanced+ Boot Block Flash Memory
MT28F160C34_3.p65 鈥?Rev. 3, Pub. 8/01
WSM status can be monitored by an on-chip status reg-
ister to determine the progress of program/erase tasks.
The device is equipped with 128 bits of one time
programmable (OTP) area. The soft protection feature
for blocks will mark them as read-only by configuring soft
protection registers with command sequences.
ARCHITECTURE
The MT28F160C34 flash contains eight 4K-word
parameter blocks and thirty-one 32K-word blocks.
Memory is organized by using a blocked architecture to
allow independent erasure of selected memory blocks.
Any address within a block address range selects that
block for the required READ, WRITE, or ERASE operation
(see Figure 1).
1
漏2001, Micron Technology, Inc.
鈥?/div>
PRODUCTS
AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE
BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON鈥橲 PRODUCTION DATA SHEET SPECIFICATIONS.

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