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MT28C6428P20 Datasheet

  • MT28C6428P20

  • FLASH AND SRAM COMBO MEMORY

  • 563.39KB

  • 48頁(yè)

  • MICRON

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ADVANCE
鈥?/div>
4 MEG x 16 ASYNCHRONOUS/PAGE FLASH
512K x 16 SRAM COMBO MEMORY
FLASH AND SRAM
COMBO MEMORY
FEATURES
鈥?Flexible dual-bank architecture
鈥?Support for true concurrent operations with no
latency:
Read bank
b
during program bank
a
and vice versa
Read bank
b
during erase bank
a
and vice versa
鈥?Organization: 4,096K x 16 (Flash)
512K x 16 (SRAM)
鈥?Basic configuration:
Flash
Bank
a
(16Mb Flash for data storage)
鈥?Eight 4K-word parameter blocks
鈥?Thirty-one 32K-word blocks
Bank
b
(48Mb Flash for program storage)
鈥?Ninety-six 32K-word main blocks
SRAM
8Mb SRAM for data storage
鈥?512K-words
鈥?F_V
CC
, V
CC
Q, F_V
PP
, S_V
CC
voltages
MT28C6428P20
1.80V (MIN)/2.20V (MAX) F_V
CC
read voltage
1.80V (MIN)/2.20V (MAX) S_V
CC
read voltage
1.80V (MIN)/2.20V (MAX) V
CC
Q
MT28C6428P18
1.70V (MIN)/1.90V (MAX) F_V
CC
read voltage
1.70V (MIN)/1.90V (MAX) S_V
CC
read voltage
1.70V (MIN)/1.90V (MAX) V
CC
Q
MT28C6428P20/P18
1.80V (TYP) F_V
PP
(in-system PROGRAM/ERASE)
1.0V (MIN) S_V
CC
(SRAM data retention)
12V 鹵5% (HV) F_V
PP
(in-house programming and
accelerated programming algorithm [APA]
activation)
鈥?Asynchronous access time
Flash access time: 80ns @ 1.80V F_V
CC
SRAM access time: 80ns @ 1.80V S_V
CC
鈥?Page Mode read access
Interpage read access: 80ns @ 1.80V F_V
CC
Intrapage read access: 30ns @ 1.80V F_V
CC
鈥?Low power consumption
鈥?Enhanced suspend options
ERASE-SUSPEND-to-READ within same bank
PROGRAM-SUSPEND-to-READ within same bank
ERASE-SUSPEND-to-PROGRAM within same bank
鈥?Read/Write SRAM during program/erase of Flash
MT28C6428P20
MT28C6428P18
Low Voltage, Extended Temperature
0.18碌m Process Technology
BALL ASSIGNMENT
67-Ball FBGA (Top View)
1
A
B
C
D
E
F
G
H
NC
NC
NC
2
NC
3
A20
4
A11
5
A15
6
A14
7
A13
8
A12
9
F_V
SS
10
V
cc
Q
11
NC
12
NC
A16
A8
A10
A9
DQ15
S_WE#
DQ14
DQ7
F_WE#
NC
A21
DQ13
DQ6
DQ4
DQ5
V
SS
F_RP#
DQ12
S_CE2
S_V
CC
F_V
CC
F_WP#
F_V
PP
A19
DQ11
DQ10
DQ2
DQ3
S_LB#
S_UB#
S_OE#
DQ9
DQ8
DQ0
DQ1
A18
A17
A7
A6
A3
A2
A1
S_CE1#
F_V
CC
A5
A4
A0
F_CE#
F_V
SS
F_OE#
NC
NC
NC
Top View
(Ball Down)
鈥?Dual 64-bit chip protection registers for security
purposes
鈥?PROGRAM/ERASE cycles
100,000 WRITE/ERASE cycles per block
鈥?Cross-compatible command set support
Extended command set
Common flash interface (CFI) compliant
OPTIONS
鈥?Timing
80ns
85ns
鈥?Boot Block Configuration
Top
Bottom
鈥?Operating Voltage Range
F_V
CC
= 1.70V鈥?.90V
F_V
CC
= 1.80V鈥?.20V
鈥?Operating Temperature Range
Commercial (0
o
C to +70
o
C)
Extended (-40
o
C to +85
o
C)
鈥?Package
67-ball FBGA (8 x 8 grid)
Part Number Example:
MARKING
-80
-85
T
B
18
20
None
ET
FM
MT28C6428P20FM-80 BET
4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory
MT28C6428P20_3.p65 鈥?Rev. 3, Pub. 7/02
1
漏2002, Micron Technology, Inc.
鈥?/div>
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE
SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON鈥橲
PRODUCTION DATA SHEET SPECIFICATIONS.

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