MSP50C604
MIXED-SIGNAL PROCESSOR
SPSS028B 鈥?MAY 2000 鈥?REVISED FEBRUARY 2001
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Advanced, Integrated Speech Synthesizer
for High-Quality Sound
Operates up to 12.32 MHz (Performs up to
12 MIPS)
Slave Mode Enables Hours of Speech
Using an External Processor and Memory
Master Mode Allows 6.8 Mins of Speech
Onboard
Supports High-Quality Synthesis
Algorithms such as MELP, CELP, LPC,
ADPCM, and Polyphonic Music
Simultaneous Speech Plus Music
Capabilities
Very Low-Power Operation, Ideal for
Hand-Held Devices
Low-Voltage Operation, Sustainable by
Three (3) Batteries
Reduced Power Standby Modes, Less Than
10
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in Deep-Sleep Mode
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16 General-Purpose I/O Pins (in Master
Mode) or 4 General-Purpose I/O Pins (in
Slave Mode)
Resistor-Trimmed Oscillator or 32.768-kHz
Crystal Reference Oscillator
Slave Interface Logic
Contains 64K Bytes-Words Onboard ROM
(2K Words Reserved)
640-Word RAM
Direct Speaker Drive (32
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(PDM)
One-Bit Comparator With Edge Detection
Interrupt Service
Serial Scan Port for In-Circuit Emulation,
Monitor, and Test
Available in Die Form or 64-Pin PM Package
An Emulator Board (EPC50C604) Is
Available for Code Development in Slave
Mode
description
The MSP50C604 is a low-cost, mixed-signal processor that combines a speech synthesizer with a dedicated
slave interface logic, general-purpose I/O, onboard ROM, and direct speaker-drive in a single package. The
computational unit uses a powerful new DSP that gives the MSP50C604 unprecedented speed and
computational flexibility compared with previous devices of its type. The MSP50C604 supports a variety of
speech and audio coding algorithms, providing a range of options with respect to speech duration and sound
quality.
The device consists of a micro-DSP core, embedded program and data memory, and a self-contained clock
generation system. General-purpose periphery is comprised of 16 bits of partially configurable I/O.
The core processor is a general-purpose 16-bit microcontroller with DSP capability. The basic core block
includes a computational unit (CU), data address unit, program address unit, two timers, eight-level interrupt
processor, and several system and control registers. The core processor gives the MSP50C604 break-point
capability in emulation.
The processor is a Harvard type for efficient DSP algorithm execution, separating program and data memory
blocks to permit simultaneous access. The ROM has a protection scheme to prevent third-party pirating. It is
configured in 32K 17-bit words.
The total ROM space is divided into two areas: 1) The lower 2K words are reserved by Texas Instruments for
a built-in self-test 2) The upper 30K is for user program and data space.
The data memory is internal static RAM. The RAM is configured in 640 17-bit words. All memories are designed
to consume minimum power at a given system clock and algorithm acquisition frequency.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
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2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
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DALLAS, TEXAS 75265
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