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MSM7661B Datasheet

  • MSM7661B

  • NTSC/PAL Digital Video Decoder

  • OKI

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E2F0009-18-62
隆 Semiconductor
MSM7661B
隆 Semiconductor
NTSC/PAL Digital Video Decoder
This version:
MSM7661B
Jun. 1998
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GENERAL DESCRIPTION
The MSM7661B is an LSI device which converts digitally sampled NTSC or PAL video signals
to 8-bit format based on ITU-RBT601.
The input video signals available are composite video signals and S video signals.
The composite video signals are converted to YUV data via a 2-dimensional Y/C separation
circuit.
The A-to-D converted data is data sampled at pixel clock frequency or double pixel clock
frequency (the built-in decimation filter is used). Input signal synchronization can lock
synchronization and color burst at high speed through internal digital processing.
The MSM7661B is upward compatible with the MSM7661. It provides additional features which
are added to the MSM7661 indicated by the mark
n
and is superior to the MSM7661 in picture
quality and synchronization stability. The device, which includes an additional register added
to the MSM7661, has electrical characteristics which are nearly equal to those of the MSM7661.
The MSM7661B allows a pin-for-pin replacement with the MSM7661.
FEATURES (鈥?indicates a new feature compared with MSM7660.
n
indicates a
new feature compared with MSM7661.)
鈥?Input video signals include the following two types of digital data that are A-to-D converted
at pixel frequency or double pixel frequency :
NTSC/PAL composite video signal
NTSC/PAL S video signal
擄
8-bit Y/8-bit C (CbCr) output (conforms to ITU-RBT601)
YCbCr
4:2:2
YCbC 4 : 1 : 1
nYCbCr
8-bit multiplex output (27 MHz) (not including SAV and EAV)
鈥?2-dimensional Y/C separation using adaptive comb filter (this filter is bypassed for S video
signal input)
NTSC: 3 lines/2 lines
PAL: 2 lines (3 virtual lines)
鈥?Input signal synchronization can lock synchronization and color burst at high speed through
internal digital processing.
擄
Sampling frequency
13.5 MHz (ITU-R601)
12.27 MHz (NTSC Square Pixel)
14.31818 MHz (NTSC 4Fsc)
14.75 MHz (PAL Square Pixel)
鈥?Internal AGC/ACC circuit
Switchable between AGC and MGC (fixed gain)
nSwitchable
between ACC and MCC (fixed gain)
鈥?Built-in decimation filter located in the input stage allows easy configuration of an external
filter circuit (located ahead of A/D converter).
鈥?Automatic NTSC/PAL recognition (only for ITU-RBT.601)
鈥?Sleep mode
1/42

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