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MSM5718C50 Datasheet

  • MSM5718C50

  • 18Mb (2M x 9) & 64Mb (8M x 8) Concurrent RDRAM

  • 46頁

  • OKI

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E2G1059-39-21
隆 Semiconductor
MSM5718C50/MD5764802
隆 Semiconductor
18Mb (2M
樓
9) & 64Mb (8M
樓
8) Concurrent RDRAM
This version: Feb. 1999
MSM5718C50/MD5764802
Previous version: Nov. 1998
DESCRIPTION
The 18/64-Megabit Concurrent Rambus鈩?DRAMs (RDRAM廬) are extremely high-speed
CMOS DRAMs organized as 2M or 8M words by 8 or 9 bits. They are capable of bursting unlimited
lengths of data at 1.67 ns per byte (13.3 ns per eight bytes). The use of Rambus Signaling Level (RSL)
technology permits 600 MHz transfer rates while using conventional system and board design
methodologies. Low effective latency is attained by operating the two or four 2KB sense amplifiers
as high speed caches, and by using random access mode (page mode) to facilitate large block
transfers. Concurrent (simultaneous) bank operations permit high effective bandwidth using
interleaved transactions.
RDRAMs are general purpose high-performance memory devices suitable for use in a broad range
of applications including PC and consumer main memory, graphics, video, and any other
application where high-performance at low cost is required.
FEATURES
鈥?Compatible with Base RDRAMs
鈥?600 MB/s peak transfer rate per RDRAM
鈥?Rambus Signaling Level (RSL) interface
鈥?Synchronous, concurrent protocol for block-oriented, interleaved (overlapped) transfers
鈥?480 MB/s effective bandwidth for random 32 byte transfers from one RDRAM
鈥?13 active signals require just 32 total pins on the controller interface (including power)
鈥?3.3 V operation
鈥?Additional/multiple Rambus Channels each provide an additional 600 MB/s bandwidth
鈥?Two or four 2KByte sense amplifiers may be operated as caches for low latency access
鈥?Random access mode enables any burst order at full bandwidth within a page
鈥?Graphics features include write-per-bit and mask-per-bit operations
鈥?Available in horizontal surface mount plastic package (SHP32-P-1125-0.65-K)
1/45

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