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131,072-words
樓
32 bits
樓
2 banks memory
Single 3.3 V鹵0.3 V power supply
LVTTL compatible inputs and outputs
All input signals are latched at rising edge of system clock
Auto precharge and controlled precharge
Internal pipelined operation: column address can be changed every clock cycle
Dual internal banks controlled by A9 (Bank Address: BA)
Independent byte operation via DQM0 to DQM3
Simplified function (No Block write, Write per bit, Single write and Burst stop)
Programmable burst sequence (Sequential / Interleave)
Programmable burst length (1, 2, 4, 8 and full page)
Programmable
CAS
latency (1, 2 and 3)
Power Down operation and Clock Suspend operation
Auto refresh and Self refresh capability
1,024 refresh cycle / 16 ms
Package :
100-pin plastic QFP
(QFP100-P-1420-0.65-BK4)
(Product : MSM54V24632A-xxGS-BK4)
xx indicates speed rank.
PRODUCT FAMILY
Family
MSM54V24632A-8
MSM54V24632A-10
MSM54V24632A-12
Clock Frequency
MHz (Max.)
125
100
83
100-pin Plastic QFP (14
樓
20 mm)
Package
1