E2L0017-17-Y1
隆 Semiconductor
MSM548263
隆 Semiconductor
262,144-Word
樓
8-Bit Multiport DRAM
This version: Jan. 1998
MSM548263
Previous version: Dec. 1996
DESCRIPTION
The MSM548263 is a 2-Mbit CMOS multiport DRAM composed of a 262,144-word by 8-bit
dynamic RAM, and a 512-word by 8-bit SAM. Its RAM and SAM operate independently and
asynchronously.
It supports three types of operations: random access to RAM port, high speed serial access to
SAM port, and bidirectional transfer of data between any selected row in the RAM port and the
SAM port. In addition to the conventional multiport DRAM operating modes, the MSM548263
features block write, flash write functions and extended page mode on the RAM port and a split
data transfer capability, programmable stops on the SAM port. The SAM port requires no refresh
operation because it uses static CMOS flip-flops.
FEATURES
鈥?Single power supply: 5 V
鹵10%
鈥?/div>
RAS
only refresh
鈥?Full TTL compatibility
鈥?/div>
CAS
before
RAS
refresh
鈥?Multiport organization
鈥?Hidden refresh
RAM : 256K word
樓
8 bits
鈥?Serial read/write
SAM : 512 word
樓
8 bits
鈥?512 tap location
鈥?Extended page mode
鈥?Programmable stops
鈥?Write per bit
鈥?Bidirectional data transfer
鈥?Persistent write per bit
鈥?Split transfer
鈥?Masked flash write
鈥?Masked write transfer
鈥?Masked block write
鈥?Refresh: 512 cycles/8 ms
鈥?Package options:
40-pin 400 mil plastic SOJ
(SOJ40-P-400-1.27)
(Product : MSM548263-xxJS)
44/40-pin 400 mil plastic TSOP (Type II)(TSOPII44/40-P-400-0.80-K)(Product : MSM548263-xxTS-K)
xx indicates speed rank.
PRODUCT FAMILY
Family
MSM548263-60
MSM548263-70
MSM548263-80
Access Time
RAM
60 ns
70 ns
80 ns
SAM
17 ns
17 ns
20 ns
Cycle Time
RAM
120 ns
140 ns
150 ns
SAM
22 ns
22 ns
25 ns
Power Dissipation
Operating
140 mA
130 mA
120 mA
Standby
8 mA
8 mA
8 mA
1/40
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