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MRFIC2006 Datasheet

  • MRFIC2006

  • 900 MHz 2 STAGE PA SILICON MONOLITHIC INTEGRATED CIRCUIT

  • 169.18KB

  • 8頁(yè)

  • MOTOROLA   MOTOROLA

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MRFIC2006/D
The MRFIC Line
900 MHz 2 Stage PA
The MRFIC2006 is an Integrated PA designed for linear operation in the 800
MHz to 1.0 GHz frequency range. The design utilizes Motorola鈥檚 advanced
MOSAIC 3 silicon bipolar RF process to yield superior performance in a cost
effective monolithic device. Applications for the MRFIC2006 include CT-1 and
CT-2 cordless telephones, remote controls, video and audio short range links,
low cost cellular radios, and ISM band transmitters.
鈥?/div>
50
鈩?/div>
Input and Output Impedance
鈥?/div>
Typical Gain = 23 dB @ 900 MHz
鈥?/div>
Bias Current Externally Adjustable
鈥?/div>
Bias Pin can be used to Ramp or Disable
鈥?/div>
Class A or AB Linear Operation
鈥?/div>
Unconditionally Stable
鈥?/div>
SO-8 Leaded Plastic Package
鈥?/div>
Order MRFIC2006R2 for Tape and Reel.
R2 Suffix = 2,500 Units per 12 mm, 13 inch Reel.
鈥?/div>
Device Marking = M2006
MRFIC2006
900 MHz 2 STAGE PA
SILICON MONOLITHIC
INTEGRATED CIRCUIT
CASE 751-05
(SO-8)
ABSOLUTE MAXIMUM RATINGS
(TA = 25擄C, Zo = 50
鈩?/div>
unless otherwise noted)
Rating
Supply Voltages
Bias Voltage
Total Supply Current
RF Output Power (VCC2
<
4.0 V)
RF Output Power (4.0 V
<
VCC2
鈮?/div>
5.0 V)
RF Input Power
Operating Ambient Temperature
Storage and Junction Temperature
Thermal Resistance, Junction to Case
Symbol
VCC1, VCC2
Vbias
ICC1, ICC2
Pout
Pout
Pin
TA
Tstg
R
胃JC
Value
5.0
6.0
100
+21
53 鈥?8 VCC2
+10
鈥?35 to + 85
鈥?65 to +150
63
Unit
Vdc
Vdc
mA
dBm
dBm
dBm
擄C
擄C
擄C/W
GND
4
GND
3
GND
2
RF OUT (VCC2)
1
5
RF IN
6
GND
7
VCC1
8
Vbias
Pin Connections and Functional Block Diagram
REV 2
MOTOROLA RF DEVICE DATA
Motorola, Inc. 1997
MRFIC2006
1

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