MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MRFIC1502/D
The MRFIC Line
Integrated GPS Downconverter
This integrated circuit is intended for GPS receiver applications. The dual
conversion design is implemented in Motorola鈥檚 low鈥揷ost high performance
MOSAIC 3 silicon bipolar process and is packaged in a low鈥揷ost surface mount
TQFP鈥?8 package. In addition to the mixers, a VCO, a PLL and a loop filter are
integrated on鈥揷hip. Output IF is nominally 9.5 MHz.
鈥?/div>
65 dB Minimum Conversion Gain
鈥?/div>
5 Volts Operation
鈥?/div>
50 mA Typical Current Consumption
鈥?/div>
Low鈥揅ost, Low Profile Plastic TQFP Package
鈥?/div>
Device Marking = M1502
MRFIC1502
1.575 GHz GPS
DOWNCONVERTER
CASE 932鈥?2
(TQFP鈥?8)
GND
48
GND
VCO VT
GND
VCC5
GND
VCO CE
GND
SF CAP1
GND
1
2
3
4
5
6
7
8
9
GND
47
GND
46
GND
45
RF IN GND VCC1 GND
44
43
42
41
TO
BPF
40
FROM
BPF GND
39
38
GND
37
36
35
34
33
GND
38 MHz TRAP
38 MHz TRAP
BYPASS CAP
IF OUT
VCC2
GND
TQFP鈥?8
ACTIVE
FILTER
VCO
40
2
32
31
30
29 GAIN CONTROL
LOOP
FILTER
28 VCC3
27 GND
26 GND
25 GND
13
C2A
14
C2B
15
C1
16
CA
17
CB
18
DCX0
19
20
21
CLK
OUT
22
GND
23
GND
24
GND
PHASE
DETECTOR
SF CAP2 10
GND 11
GND 12
VCC4 GND
Pin Connections and Functional Block Diagram
漏
Motorola, Inc. 1997
MOTOROLA RF DEVICE DATA
MRFIC1502
1
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