MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MRFIC0914/D
The MRFIC Line
900 MHz LDMOS Integrated
Power Amplifier
MRFIC0914
900 MHz PAGING
POWER AMPLIFIER
Si MONOLITHIC
INTEGRATED CIRCUIT
This integrated circuit is intended for two鈥搘ay paging applications and for
other Industrial, Scientific and Medical (ISM) at 900 MHz band applications.
The three stage design is implemented in Motorola鈥檚 low cost, high perfor-
mance LDMOS process and housed in a low鈥揷ost surface mount SOIC
package. Input and output matching is implemented off鈥揷hip for maximum
flexibility while interstage matching is on鈥揷hip. A power control pin is included
allowing 60 dB dynamic range.
鈥?/div>
30.5 dBm Output Power for 3 dBm Input Power at 900 MHz
鈥?/div>
32 dB Typ Small Signal Gain
鈥?/div>
40% Efficiency Min at 30.5 dBm Output Power
鈥?/div>
4.0 to 5.5 Volt Operation
鈥?/div>
Low鈥揅ost, Low Profile Plastic SOIC Package
鈥?/div>
Order MRFIC0914R2 for Tape and Reel.
R2 Suffix = 2,500 Units per 16 mm, 13 inch Reel.
鈥?/div>
Device Marking = M0914
CASE 751B鈥?5
(SOIC鈥?6)
ABSOLUTE MAXIMUM RATINGS
(TA = 25擄C unless otherwise noted)
Rating
Supply Voltage
Supply Current
Power Control Voltage
Input Power
Ambient Operating Temperature
Storage Temperature
Thermal Resistance, Junction to Case
Symbol
VD1, VD2, VD3
IDtotal
VCNTRL
Pin
TA
Tstg
胃
JC
Value
9
2
4.8
6
鈥?30 to + 80
鈥?65 to +150
26
Unit
Vdc
Adc
Vdc
dBm
擄C
擄C
擄C/W
VCNTRL
GND
VD2
GND
GND
RF OUT/VD3
GND
GND
1
CONTROL
2
3
4
5
6
7
8
16 GND
15 GND
14 RF IN
13 GND
12 GND
11 VD1
10 GND
9
GND
Pin Connections and Functional Block Diagram
REV 2
MOTOROLA RF
漏
Motorola, Inc. 1997
DEVICE DATA
MRFIC0914
1
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