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MR27V3266D Datasheet

  • MR27V3266D

  • 2M x16 / 1M x32 Synchronous OTP ROM

  • 234.33KB

  • 36頁

  • OKI

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1
Semiconductor
MR27V3266D
2M x16 / 1M x32 Synchronous OTP ROM
DESCRIPTION
The MR27V3266D is a 32Mbit One Time Programmable Synchronous Read Only Memory whose configuration
can be electrically switched between 2,097,152 x16bit(word mode) and 1,048,576 x32bit(double word mode) by
the state of the /WORD pin. The MR27V3266D supports high speed synchronous read operations using a single
3.3V power supply.
FEATURES ON READ
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3.3V power supply
LVTTL compatible with multiplexed address
Dual, electrically switchable configurations
2M x16(word mode) / 1M x32(double word mode)
All inputs are sampled at the rising edge of the system clock
High speed read operation
66MHz : CAS Latency=5
tRCDmin=2
Burst Length (4, 8)
Data scramble (sequential, interleave)
50MHz : CAS Latency=4, 5
tRCDmin=1
Burst Length (4, 8)
Data scramble (sequential, interleave)
DQM for data out masking
No Precharge operation is required. No Refresh operation is required.
No power on sequence is required.
Mode register is automatically initialized to the default state after power on.
"Row Active" command to read data is applicable as the first command just after power on.
Single Bank operation
Package : TSOP II 86-P-400-0.50-K
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FEATURES ON PROGRAMMING
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9.75V programming Power supply
Programming algorithm is compatible with conventional asynchronous 32M OTP.
MR27V3266D can be programmed with conventional EPROM programmers.
Synchronous Burst read or Static Programming Operation are selected by the state of STO pin.
High STO level enables full static programming. (Program, Program Verify, asynchronous Read)
Low STO level enables synchronous burst read.
Exclusive 86pin socket adapters are available from OKI to support programming requirements.
The socket adapter is used on a 48DIP socket on the programmer.
The socket adapter is designed with the STO pin connected to V
CC
in order to program MR27V3266D
as conventional 32M OTP.
EPROM programmer must have the proper algorithm for 32M OTP.
*Device damage can occur if improper algorithm is used.
High speed programming
10碌s programming pulse per word allows high speed programming.
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August , 1999
Revision 2.4
1
32M Synchronous OTP

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