鈥?/div>
Floating Channel Designed for Bootstrap Operation
Fully Operational to +600 V
Tolerant to Negative Transient Voltage
dV/dt Immune
Gate Drive Supply Range from 10 to 20 V
Undervoltage Lockout for Both Channels
Separate Logic Supply
Operating Supply Range from 5 to 20 V
Logic and Power Ground Operating Offset Range from 鈥? to +5 V
CMOS Schmitt鈥搕riggered Inputs with Pull鈥揹own
Cycle by Cycle Edge鈥搕riggered Shutdown Logic
Matched Propagation Delay for Both Channels
Outputs In Phase with Inputs
PRODUCT SUMMARY
P SUFFIX
PLASTIC PACKAGE
CASE 646鈥?6
16
1
DW SUFFIX
PLASTIC PACKAGE
CASE 751G鈥?2
SOIC 鈥?WIDE
ORDERING INFORMATION
Device
MPIC2113DW
MPIC2113P
Package
SOIC WIDE
PDIP
VOFFSET
IO+/鈥?/div>
VOUT
ton/off (typical)
Delay Matching
600 V MAX
2 A/2 A
10 鈥?20 V
120 & 94 ns
10 ns
PIN CONNECTIONS
(TOP VIEW)
9
8
9
10
11
12
13
14
VDD
HIN
SD
LIN
VSS
VCC
COM
LO
HO
VB
VS
7
6
5
4
3
2
1
10
11
12
13
14
15
16
VDD
HIN
SD
LIN
VSS
VCC
COM
LO
HO
VB
VS
8
7
6
5
4
3
2
1
14 LEADS PDIP MPIC2113P
16 LEADS SOIC (WIDE BODY)
MPIC2113DW
This document contains information on a new product. Specifications and information herein are subject
to change without notice.
漏
Motorola TMOS
Motorola, Inc. 1996
Power MOSFET Transistor Device Data
1
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