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MPD705101 Datasheet

  • MPD705101

  • V831TM 32-BIT MICROPROCESSOR

  • 294.51KB

  • 72頁(yè)

  • NEC   NEC

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DATA SHEET
MOS INTEGRATED CIRCUIT
碌
PD705101
V831
TM
32-BIT MICROPROCESSOR
DESCRIPTION
The
碌
PD70501 (V831) is a 32-bit RISC microprocessor for embedded control applications, with a high-performance
32-bit V830
TM
processor core and many peripheral functions such as a DRAM/ROM controller, 4-channel DMA
controller, real-time pulse unit, serial interface, and interrupt controller.
In addition to high interrupt response speed and optimized pipeline structure, the V831 offers sum-of-products
operation instructions, concatenated shift instructions, and high-speed branch instructions to realize multimedia
functions, and therefore, can provide high performance in multimedia systems such as internet/intra-net systems, car
navigation systems, high-performance televisions, and color FAXes.
Detailed explanations of the functions, etc. are given in the following user鈥檚 manuals. Be sure to read the
manuals before designing your systems.
V831 User鈥檚 Manual -Handware
: U12273E
V830 Family
TM
User鈥檚 Manual -Architecture : U12496E
FEATURES
鈥?CPU function
鈥?V830-compatible instructions
鈥?Instruction cache
鈥?Instruction RAM
鈥?Data cache
鈥?Data RAM
鈥?Minimum number of instruction
execution cycles
鈥?Number of general purpose
registers
鈥?Memory space and I/O space
鈥?Interrupt/exception function
鈥?Non-maskable : External input : 1
鈥?Maskable
: External input : 8 (of which 4 are
multiplexed with internal sources)
Internal source: 11 types
鈥?/div>
鈥?/div>
鈥?/div>
Bus control function
Wait control function
Memory access control function
: 32 bits
脳
32
: 4 GB each
: 1 cycle
: 4 KB
: 4 KB
: 4 KB
: 4 KB
鈥?/div>
鈥?/div>
DMA controller
: 4 channel
Serial interface function
鈥?Asynchronous serial interface (UART): 1 channel
鈥?Clocked serial interface (CSI)
: 1 channel
鈥?Dedicated baud rate generator (BRG) : 1 channel
鈥?/div>
Timer/counter function
鈥?16-bit timer/event counter : 1 channel
鈥?16-bit interval timer
: 1 channel
: 3 I/O ports
: HALT and STOP modes
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Port function
Standby function
Debug function
Clock generation function : PLL clock synthesizer
鈥?Debug-dedicated synchronous serial
interface
鈥?Trace-dedicated interface
: 1 channel
: 1 channel
The information in this document is subject to change without notice.
Document No. U12979EJ1V0DS00 (1st edition)
Date Published January 1998 N
Printed in Japan
漏
1998

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