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MPC99J93 Datasheet

  • MPC99J93

  • Intelligent Dynamic Clock Switch (IDCS) PLL Clock Driver

  • 8頁(yè)

  • MOTOROLA   MOTOROLA

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MOTOROLA
Freescale
SEMICONDUCTOR TECHNICAL DATA
Semiconductor, Inc.
Order Number: MPC99J93/D
Rev 1, 08/2003
Product Preview
Intelligent Dynamic Clock
Switch (IDCS) PLL Clock
Driver
The MPC99J93 is a PLL clock driver designed specifically for redun-
dant clock tree designs. The device receives two differential LVPECL
clock signals from which it generates 5 new differential LVPECL clock
outputs. Two of the output pairs regenerate the input signals frequency
and phase while the other three pairs generate 2x, phase aligned clock
outputs.
Features:
鈥?/div>
Fully Integrated PLL
MPC99J93
Freescale Semiconductor, Inc...
FA SUFFIX
32--LEAD LQFP PACKAGE
CASE 873A
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Intelligent Dynamic Clock Switch
LVPECL Clock Outputs
LVCMOS Control I/O
3.3V Operation
32--Lead LQFP Packaging
Functional Description
The MPC99J93 Intelligent Dynamic Clock Switch (IDCS) circuit continuously monitors both input CLK signals. Upon detection
of a failure (CLK stuck HIGH or LOW for at least 1 period), the INP_BAD for that CLK will be latched (H). If that CLK is the primary
clock, the IDCS will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase
disturbance. The typical phase bump caused by a failed clock is eliminated. (See Application Information section).
PLL_En
Clk_Selected
Inp1bad
Inp0bad
Man_Override
Alarm_Reset
Sel_Clk
CLK0
CLK0
CLK1
CLK1
Ext_FB
Ext_FB
MR
OR
Dynamic Switch
Logic
Qb0
Qb0
Qb1
Qb1
梅2
PLL
200 -- 360 MHz
梅4
Qb2
Qb2
Qa0
Qa0
Qa1
Qa1
Figure 1. Block Diagram
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
E
Motorola Inc. 2003
MOTOROLA TIMING SOLUTIONS
1
For More Information On This Product,
Go to: www.freescale.com

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