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MPC992 Datasheet

  • MPC992

  • LOW VOLTAGE PLL CLOCK DRIVER

  • 8頁(yè)

  • MOTOROLA   MOTOROLA

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Low Voltage PECL PLL Clock
Driver
The MPC992 is a 3.3V compatible, PLL based PECL clock generator
and distributor. The fully differential design ensures optimum skew and
PLL jitter performance. The performance of the device makes the
MPC992 ideal for workstations, main frame computer, telecommunication
and instrumentation applications. The device offers a crystal oscillator or
a differential PECL reference clock input to provide flexibility in the
reference clock interface. All of the control signals to the MPC992 are
LVTTL compatible inputs.
MPC992
LOW VOLTAGE
PLL CLOCK DRIVER
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Fully Integrated PLL
Output Frequency of up to 400MHz
PECL Clock Inputs and Outputs
Operates from a 3.3V VCC Supply
Output Frequency Configurable
32 TQFP Packaging
鹵25ps
Cycle鈥揅ycle Jitter
FA SUFFIX
PLASTIC TQFP PACKAGE
CASE 873A-02
The MPC992 offers two banks of outputs which can be configured into
four different relationships. The output banks can be configured into 2:1,
3:1, 3:2 and 5:2 ratios to provide a wide variety of potential frequency
outputs. In addition to these two banks of outputs a synchronization output is also offered. The SYNC output will provide
information as to the time when the two output banks will transition positively in phase. This information can be important when
the odd ratios are used as it provides for a baseline point in the system timing. The SYNC output will pulse high for one Qa clock
period, centered on the rising Qa clock edge four edges prior to the Qb synchronous edge. The relationship is illustrated in the
timing diagrams in the data sheet.
The MPC992 offers several features to aid in system debug and test. The PECL reference input pins can be interfaced to a test
signal and the PLL can be bypassed to allow the designer to drive the MPC992 outputs directly. This allows for single stepping in
a system functional debug mode. In addition an overriding reset is provided which will force all of the Q outputs LOW upon
assertion.
The MPC992 is packaged in a 32鈥搇ead TQFP package to optimize both performance and board density.
MPC992 LOGIC DIAGRAM
PLL_EN
VCO_SEL
XTAL_SEL
XTAL1
XTAL2
PECL_CLK
PECL_CLK
FSEL0
FSEL1
POR
XTAL
OSC
x2
1
0
Integrated
PLL
0
1
0
1
Qan
Qan
Frequency
Generator
Qbn
Qbn
SYNC
SYNC
(x4)
(x3)
Reset
(x1)
7/96
漏
Motorola, Inc. 1996
1
REV 1

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