鈥?/div>
Fully Integrated PLL
Two Reference Clock Inputs for Redundant Clock Applications
High Impedance Output Control
Logic Enable on the Outputs
3.3V VCC Supply
Output Frequency Configurable
TQFP Packaging
鹵100ps
Typical Cycle鈥搕o鈥揅ycle Jitter
LOW VOLTAGE
PLL CLOCK DRIVER
The MPC974 features 3 independent frequency programmable banks
of outputs. The frequency programmability offers the capability of
establishing output frequency relationships of 1:1, 2:1, 3:1, 3:2 and 3:2:1.
In addition, the device features a separate feedback output which allows
for a wide variety of input/output frequency multiplication alternatives.
FA SUFFIX
The VCO_Sel pin provides an extended VCO lock range for added
52鈥揕EAD TQFP PACKAGE
flexibility and general purpose usage.
CASE 848D-03
The TCLK0 and TCLK1 inputs provide a method for dynamically
switching the PLL between two different clock sources. The PLL has been
optimized to provide small deviations in output pulse width and well
controlled, slow transition back to lock when the inputs are switched
between two references that are equal in frequency but out of phase with
each other. This feature makes the MPC974 an ideal solution for fault
tolerant applications which require redundant clock sources.
All of the control pins are LVTTL/LVCMOS level inputs. The Fsel pins control the VCO divide ratios that are applied to the
various output banks and the feedback output. The MR input will reset the internal flip flops and place the outputs in high
impedance when driven LOW. The OE pin will force all of the outputs except the feedback output LOW to allow for acquiring
phase lock prior to providing clocks to the rest of the system. Note that the OE pin is not synchronized to the internal clock. As a
result, the initial pulse after de鈥揳ssertion of the OE pin may be distorted. The PLL_En pin allows the PLL to be bypassed for
board level functional test. When bypassed the signal on the selected TCLK will be routed around the PLL and will drive the
internal dividers directly.
The MPC974 is packaged in the 52鈥搇ead TQFP package to provide optimum electrical performance as well as minimize board
space requirements. The device is specified for 3.3V VCC.
1/97
漏
Motorola, Inc. 1997
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