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Pin and function compatible to MPC949
Functional Description
The MPC9449 is specifically designed to distribute LVCMOS
compatible clock signals up to a frequency of 200 MHz. The device has
15 identical outputs, organized in 4 output banks. Each output bank
provides a retimed or frequency divided copy of the input signal with a
near zero skew. The output buffer supports driving of 50鈩?terminated
transmission lines on the incident edge: each output is capable of driving
either one parallel terminated or two series terminated transmission lines.
Two selectable LVCMOS compatible clock inputs are available. This feature supports redundant differential clock sources. In
addition, the MPC9449 accepts one differential PECL clock signal. The DSELx pins choose between division of the input
reference frequency by one or two. The frequency divider can be set individually for each of the four output banks. Applying the
OE control will force the outputs into high-impedance mode.
All inputs have an internal pull-up or pull-down resistor preventing unused and open inputs from floating. The device supports a
2.5V or 3.3V power supply and an ambient temperature range of 鈥?0擄C to +85擄C. The MPC9449 is pin and function compatible
but performance-enhanced to the MPC949. The device is packaged in a 52-lead LQFP package.
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Maximum clock frequency of 200 MHz
Maximum clock skew of 200 ps
High-impedance output control
3.3V or 2.5V power supply
Drives up to 30 series terminated clock lines
Ambient temperature range 鈥?0擄C to +85擄C
52 lead LQFP packaging
漏
Motorola, Inc. 2002
For More Information On This Product,
1
Go to: www.freescale.com
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