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12 LVCMOS compatible clock outputs
Selectable LVCMOS and differential LVPECL compatible clock inputs
Maximum clock frequency of 350 MHz
Maximum clock skew of 150 ps
Synchronous output stop in logic low state eliminates output runt pulses
High--impedance output control
3.3V or 2.5V power supply
Drives up to 24 series terminated clock lines
Ambient temperature range --40擄C to +85擄C
32--Lead LQFP packaging
LOW VOLTAGE
3.3V/2.5V LVCMOS 1:12
CLOCK FANOUT BUFFER
Supports clock distribution in networking, telecommunication and
computing applications
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Pin and function compatible to MPC948
FA SUFFIX
32--LEAD LQFP PACKAGE
CASE 873A
Functional Description
The MPC9448 is specifically designed to distribute LVCMOS
compatible clock signals up to a frequency of 350 MHz. Each output
provides a precise copy of the input signal with a near zero skew. The
outputs buffers support driving of 50鈩?terminated transmission lines on
the incident edge: each output is capable of driving either one parallel
terminated or two series terminated transmission lines.
Two selectable, independent clock inputs are available, providing support of LVCMOS and differential LVPECL clock
distribution systems. The MPC9448 CLK_STOP control is synchronous to the falling edge of the input clock. It allows the start
and stop of the output clock signal only in a logic low state, thus eliminating potential output runt pulses. Applying the OE control
will force the outputs into high--impedance mode.
All inputs have an internal pull--up or pull--down resistor preventing unused and open inputs from floating. The device supports
a 2.5V or 3.3V power supply and an ambient temperature range of --40擄C to +85擄C. The MPC9448 is pin and function compatible
but performance--enhanced to the MPC948.
漏
Motorola, Inc. 2003
For More Information On This Product,
Go to: www.freescale.com
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