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Freescale Semiconductor, Inc.

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order number: MPC92432

Rev 0, 06/2004

Product Preview

1360 MHz Dual Output LVPECL

Clock Synthesizer

The MPC92432 is a 3.3V compatible, PLL based clock synthesizer targeted

for high performance clock generation in mid-range to high-performance

telecom, networking, and computing applications. With output frequencies

from 21.25 MHz to 1360 MHz and the support of two differential PECL output

signals, the device meets the needs of the most demanding clock applications.

Features

MPC92432

1360 MHz LOW VOLTAGE

CLOCK SYNTHESIZER

Freescale Semiconductor, Inc...

鈥?/div>

21.25 MHz to 1360 MHz synthesized clock output signal

Two differential, LVPECL-compatible high-frequency outputs

Output frequency programmable through 2-wire I

2

C bus or parallel

interface

On-chip crystal oscillator for reference frequency generation

Alternative LVCMOS compatible reference clock input

Synchronous clock stop functionality for both outputs

LOCK indicator output (LVCMOS)

LVCMOS compatible control inputs

Fully integrated PLL

3.3-V power supply

48-lead LQFP

SiGe Technology

Ambient temperature range: 鈥?0擄C to +85擄C

SCALE 2:1

FA SUFFIX

48-LEAD LQFP PACKAGE

CASE 932

Applications

鈥?Programmable clock source for server, computing, and telecommunication systems

鈥?Frequency margining

鈥?Oscillator replacement

Functional Description

The MPC92432 is a programmable high-frequency clock source (clock synthesizer). The internal PLL generates a high-frequency

output signal based on a low-frequency reference signal. The frequency of the output signal is programmable and can be changed

on the fly for frequency margining purpose.

The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. Alternatively, a LVCMOS com-

patible clock signal can be used as a PLL reference signal. The frequency of the internal crystal oscillator is divided by a selectable

divider and then multiplied by the PLL. The VCO within the PLL operates over a range of 1360 to 2720 MHz. Its output is scaled by

a divider that is configured by either the I

2

C or parallel interfaces. The crystal oscillator frequency f

XTAL

, the PLL pre-divider P, the

feedback-divider M, and the PLL post-divider N determine the output frequency. The feedback path of the PLL is internal.

The PLL post-divider N is configured through either the I

2

C or the parallel interfaces, and can provide one of six division ratios (2,

4, 8, 16, 32, 64). This divider extends the performance of the part while providing a 50% duty cycle. The high-frequency outputs, Q

A

and Q

B

, are differential and are capable of driving a pair of transmission lines terminated 50

鈩?/div>

to V

CC

鈥?2.0 V. The second high-fre-

quency output, Q

B

, can be configured to run at either 1x or 1/2x of the clock frequency or the first output (Q

A

). The positive supply

voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize noise induced jitter.

The configuration logic has two sections: I

2

C and parallel. The parallel interface uses the values at the M[9:0], NA[2:0], NB, and P

parallel inputs to configure the internal PLL dividers. The parallel programming interface has priority over the serial I

2

C interface. The

serial interface is I

2

C compatible and provides read and write access to the internal PLL configuration registers. The lock state of the

PLL is indicated by the LVCMOS-compatible LOCK outputs.

This document contains certain information on a new product.

Specifications and information herein are subject to change without notice

.

漏 Motorola, Inc. 2004

For More Information On This Product,

Go to: www.freescale.com

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