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MOTOROLA

MPC561PB/D

Rev. 1, December 2001

SEMICONDUCTOR

PRODUCT BRIEF

MPC561/MPC562

MPC563/MPC564

Product Brief

MPC561/MPC562 / MPC563/MPC564 RISC MCU

Including Peripheral Pin Multiplexing with

Flash and Code Compression Options

Features

The MPC561/MPC562 / MPC563/MPC564 are members of the Motorola MPC500 RISC Microcontroller

family. As shown in the block diagram, they are composed of:

鈥?High performance CPU system

鈥?High performance core

鈥?Single issue integer core

鈥?Compatible with PowerPC instruction set architecture

鈥?Precise exception model

鈥?Floating point

鈥?Extensive system development support

鈥?On-chip watchpoints and breakpoints

鈥?Program flow tracking

鈥?Background debug mode (BDM)

鈥?IEEE-ISTO Nexus 5001-1999 Class 3 Debug Interface

鈥?MPC500 system interface (USIU, BBC, L2U)

鈥?Fully static design

鈥?Four major power saving modes

鈥?On, doze, sleep, deep-sleep and power-down

鈥?32-Kbyte static RAM (CALRAM)

鈥?512-Kbyte flash (UC3F) on MPC563/MPC564

鈥?General-purpose I/O support

鈥?On address (24) and data (32) pins

鈥?16 GPIO in MIOS14

鈥?Many peripheral pins can be used as GPIO when not used as primary functions

鈥?2.6-V outputs on external bus pins

鈥?PPM (peripheral pin multiplexing with parallel-to-serial driver) module

鈥?Available in package or die

鈥?Plastic ball grid array (PBGA) packaging

Key Feature Details

MPC500 System Interface (USIU)

鈥?System configuration and protection features:

鈥?Periodic-interrupt timer

鈥?Bus monitor

鈥?Software watchdog timer

鈥?Real-time clock (RTC)

This document contains information on a new product. Specifications and

information herein are subject to change without notice.

漏 MOTOROLA 2001, All Rights Reserved

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